PowerPC 601 RISC Microprocessor Technical Summary

3

•

High instruction and data throughput

— Zero-cycle branch capability

— Programmable static branch prediction on unresolved conditional branches

— Instruction unit capable of fetching eight instructions per clock from the cache

— An eight-entry instruction queue that provides look-ahead capability

— Interlocked pipelines with feed-forwarding that control data dependencies in hardware

— Unified 32-Kbyte cache—eight-way set-associative, physically addressed; LRU replacement

algorithm

— Cache write-back or write-through operation programmable on a per page or per block basis

— Memory unit with a two-element read queue and a three-element write queue

— Run-time reordering of loads and stores

— BPU that performs condition register (CR) look-ahead operations

— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte

segment size

— A 256-entry, two-way set-associative UTLB

— Four-entry BAT array providing 128-Kbyte to 8-Mbyte blocks

— Four-entry, first-level ITLB

— Hardware table search (caused by UTLB misses) through hashed page tables

— 52-bit virtual address; 32-bit physical address

•

Facilities for enhanced system performance

— Bus speed defined as selectable division of operating frequency

— A 64-bit split-transaction external data bus with burst transfers

— Support for address pipelining and limited out-of-order bus transactions

— Snooped copyback queues for cache block (sector) copyback operations

— Bus extensions for I/O controller interface operations

— Multiprocessing support features that include the following:

–

Hardware enforced, four-state cache coherency protocol (MESI)

–

Separate port into cache tags for bus snooping

•

In-system testability and debugging features through boundary-scan capability

1.2 Block Diagram

Figure 1 provides a block diagram of the 601 that illustrates how the execution units—IU, FPU, and BPU—

operate independently and in parallel.

The 601's 32-Kbyte, unified cache tag directory has a port dedicated to snooping bus transactions,

preventing interference with processor access to the cache. The 601 also provides address translation and

protection facilities, including a UTLB and a BAT array, and a four-entry ITLB that contains the four most

recently used instruction address translations for fast access by the instruction unit.

Instruction fetching and issuing is handled in the instruction unit. Translation of addresses for cache or

external memory accesses are handled by the memory management unit. Both units are disc

ussed in more

detail in Sections 1.3, “Instruction Unit,” and 1.5, “Memory Management Unit (MMU).”

Freescale Semiconductor, Inc.

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Go to: www.freescale.com

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