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PowerPC 601 RISC Microprocessor Technical Summary

The BPU contains an adder to compute branch target addresses and three special-purpose, user-control

registers—the link register (LR), the count register (CTR), and the CR. The BPU calculates the return

pointer for subroutine calls and saves it into the LR for certain types of branch instructions. The LR also

contains the branch target address for the Branch Conditional to Link Register (bclrx) instruction. The CTR

contains the branch target address for the Branch Conditional to Count Register (bcctrx) instruction. The

contents of the LR and CTR can be copied to or from any GPR. Because the BPU uses dedicated registers

rather than general-purpose or floating-point registers, execution of branch instructions is largely

independent from execution of integer and floating-point instructions.

1.4.2 Integer Unit (IU)

The IU executes all integer instructions and executes floating-point memory accesses in concert with the

FPU. The IU executes one integer instruction at a time, performing computations with its arithmetic logic

unit (ALU), multiplier, divider, integer exception register (XER), and the general-purpose register file. Most

integer instructions are single-cycle instructions.

The IU interfaces with the cache and MMU for all instructions that access memory. Addresses are formed

by adding the source 1 register operand specified by the instruction (or zero) to either a source 2 register

operand or to a 16-bit, immediate value embedded in the instruction.

Load and store instructions are issued and translated in program order; however, the accesses can occur out

of order. Synchronizing instructions are provided to enforce strict ordering.

Load and store instructions are considered to have completed execution with respect to precise exceptions

after the address is translated. If the address for a load or store instruction hits in the UTLB or BAT array

and it is aligned, the instruction execution (that is, calculation of the address) takes one clock cycle, allowing

back-to-back issue of load and store instructions. The time required to perform the actual load or store

operation varies depending on whether the operation involves the cache, system memory, or an I/O device.

1.4.3 Floating-Point Unit (FPU)

The FPU contains a single-precision multiply-add array, the floating-point status and control register

(FPSCR), and thirty-two 64-bit FPRs. The multiply-add array allows the 601 to efficiently implement

floating-point operations such as multiply, add, divide, and multiply-add. The FPU is pipelined so that most

single-precision instructions and many double-precision instructions can be issued back-to-back. The FPU

contains two additional instruction queues. These queues allow floating-point instructions to be issued from

the instruction queue even if the FPU is busy, making instructions available for issue to the other execution

units.

Like the BPU, the FPU can access instructions from the bottom half of the instruction queue (Q3–Q0),

which permits floating-point instructions that do not depend on unexecuted instructions to be issued early

to the FPU.

The 601 supports all IEEE 754 floating-point data types (normalized, denormalized, NaN, zero, and infinity)

in hardware, eliminating the latency incurred by software exception routines.

1.5 Memory Management Unit (MMU)

The 601’s MMU supports up to 4 Petabytes (252) of virtual memory and 4 Gigabytes (232) of physical

memory. The MMU also controls access privileges for these spaces on block and page granularities.

Referenced and changed status are maintained by the processor for each page to assist implementation of a

demand-paged virtual memory system.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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