PID9v-604e Hardware Specifications

23

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

1.8.2 PLL Power Supply Filtering

The AVdd power signal is provided on the 604e to provide power to the clock generation phase-locked loop.

To ensure stability of the internal clock, the power supplied to the AVdd input signal should be filtered using

a circuit similar to the one shown in Figure 11. The circuit should be placed as close as possible to the AVdd

pin to ensure it filters out as much noise as possible.

Figure 11. PLL Power Supply Filter Circuit

1.8.3 Decoupling Recommendations

Due to the 604e’s dynamic power management feature, large address and data buses, and high operating

frequencies, the 604e can generate transient power surges and high frequency noise in its power supply,

especially while driving large capacitive loads. This noise must be prevented from reaching other

components in the 604e system, and the 604e itself requires a clean, tightly regulated source of power.

Therefore, it is recommended that the system designer place at least one decoupling capacitor at each Vdd

and OVdd pin of the 604e. It is also recommended that these decoupling capacitors receive their power from

separate Vdd, OVdd, and GND power planes in the PCB, utilizing short traces to minimize inductance.

These capacitors should vary in value from 220 pF to 10

µF to provide both high- and low-frequency

filtering, and should be placed as close as possible to their associated Vdd or OVdd pin. Suggested values

for the Vdd pins—220 pF (ceramic), 0.01

µF (ceramic), and 0.1 µF (ceramic). Suggested values for the

OVdd pins—0.01

µF (ceramic), 0.1 µF (ceramic), and 10 µF (tantalum). Only SMT (surface mount

technology) capacitors should be used to minimize lead inductance.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,

feeding the Vdd and OVdd planes, to enable quick recharging of the smaller chip capacitors. These bulk

capacitors should also have a low ESR (equivalent series resistance) rating to ensure the quick response time

necessary. They should also be connected to the power and ground planes through two vias to minimize

inductance. The suggested values for these bulk capacitors are 100

µF (AVX TPS tantalum) or 330 µF (AVX

TPS tantalum).

1.8.4 Connection Recommendations

To ensure reliable operation, it is recommended to connect unused inputs to an appropriate signal level.

Unused active low inputs should be tied to Vdd. Unused active high inputs should be connected to GND.

1.8.5 Thermal Management Information

This section provides thermal management information for the ceramic ball grid array (CBGA) package in

air-cooled applications. Proper thermal control design is primarily dependent upon the system-level

design—the heat sink, airflow and thermal interface material. To reduce the die-junction temperature, a heat

sink may be attached to the package by several methods through the use of an adhesive, a spring clip to holes

in the printed-circuit board, or a mounting clip and screw assembly; see Figure 12. For applications where

the heat sink is attached by a spring clip, the spring force should not exceed 5.5 pounds of force.

Vdd

AVdd

10

Ω

10

µF

0

.1

µF

GND

(2.5 V)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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