10

PID9v-604e Hardware Specifications

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Figure 1 provides the SYSCLK input timing diagram.

Figure 1. SYSCLK Input Timing Diagram

1.4.2.2 Input AC Specifications

Table 7 provides the input AC timing specifications as defined in Figure 2 and Figure 3 for 604e processors

operating at 166.67, 180, 200, 225, and 233 MHz core frequencies.

Table 7. Input AC Timing Specifications, 166.67–233 MHz1

Vdd = AVdd = 2.5

± 5% V dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ T

j ≤ 105 °C

Num

Characteristic

166.67 MHz

180, 200, 225,

and 233 MHz

Unit

Notes

Min

Max

Min

Max

7a

ARTRY, SHD, ABB, TS, XATS, AACK, BG,

DRTRY, TA, DBG, DBB, TEA, DBDIS, and DBWO

valid to SYSCLK (input setup)

3.5

—

3.25

—

ns

2

7b

All other inputs valid to SYSCLK (input setup)

2.25

—

2.0

—

ns

2

8

SYSCLK to all inputs invalid (input hold)

0.5

—

0.5

—

ns

9

Mode select input valid to HRESET (input setup

for DRTRY)

8 * tsysclk

—

8 * tsysclk

—

ns

3, 4, 5, 6

10

HRESET to mode select input invalid (input hold

for DRTRY)

0

—

0

—

ns

3, 4, 5, 6

Notes:

1. Input specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the 1.4 V of

the rising edge of the input SYSCLK. Input and output timings are measured at the pin (see Figure 2).

2. All other input signals include the following signals—all inputs except ARTRY, SHD, ABB, TS, XATS,

AACK, BG, DRTRY, TA, DBG, DBB, DBWO, DBDIS, TEA, and JTAG inputs.

3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3).

4. tsysclk is the period of the external clock (SYSCLK) in nanoseconds.

5. These values are guaranteed by design, and are not tested.

6. Note this is for configuration of the fast-L2 mode and the no-DRTRY mode.

VM

CVil

CVih

SYSCLK

2

3

4

VM = Midpoint Voltage (1.4 V)

4

1

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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