PID9v-604e Hardware Specifications

3

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

– 64-entry fully-associative branch target address cache (BTAC). In the 604e, the BTAC can

be disabled and invalidated.

– 512-entry branch history table (BHT) with two bits per entry for four levels of prediction—

not-taken, strongly not-taken, taken, strongly taken

— Condition register logical unit

– Two-entry reservation station

– Shares dispatch bus with BPU

— Two single-cycle IUs (SCIUs) and one multiple-cycle IU (MCIU)

– Instructions that execute in the SCIU take one cycle to execute; most instructions that

execute in the MCIU take multiple cycles to execute.

– Each SCIU has a two-entry reservation station to minimize stalls

– The MCIU has a single-entry reservation station and provides early exit (three cycles) for

16- x 32-bit and overflow operations.

– Thirty-two GPRs for integer operands

— Three-stage floating-point unit (FPU)

– Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations

– Supports non-IEEE mode for time-critical operations

– Fully pipelined, single-pass double-precision design

– Hardware support for denormalized numbers

– Two-entry reservation station to minimize stalls

– Thirty-two 64-bit FPRs for single- or double-precision operands

— Load/store unit (LSU)

– Two-entry reservation station to minimize stalls

– Single-cycle, pipelined cache access

– Dedicated adder performs effective address (EA) calculations

– Performs alignment and precision conversion for floating-point data

– Performs alignment and sign extension for integer data

– Four-entry finish load queue (FLQ) provides load miss buffering

– Six-entry store queue

– Supports both big- and little-endian modes

•

Rename buffers

— Twelve GPR rename buffers

— Eight FPR rename buffers

— Eight condition register (CR) rename buffers

•

Completion unit

— The completion unit retires an instruction from the 16-entry reorder buffer when all instructions

ahead of it have been completed and the instruction has finished execution.

— Guarantees sequential programming model (precise exception model)

— Monitors all dispatched instructions and retires them in order

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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