PID9v-604e Hardware Specifications

9

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

1.4.2.1 Clock AC Specifications

Table 6 provides the clock AC timing specifications as defined in Figure 1.

Table 6. Clock AC Timing Specifications

Vdd = AVdd = 2.5

± 5% V dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ T

j ≤ 105 °C

Num

Characteristic

166.67

MHz

180

MHz

200

MHz

225

MHz

233

MHz

Unit

Notes

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Processor

frequency

83.3 166.7

90

180

100

200

112

225

116

233

MHz

1

VCO frequency

166

33

180

360

200

400

225

450

233

466

MHz

1

SYSCLK (bus)

frequency

25

66

25

66

25

66

25

75

25

75

MHz

1, 6

1

SYSCLK cycle

time

15

40

15

40

15

40

13

40

13

40

ns

2, 3

SYSCLK rise and

fall time

1.0

2.0

1.0

2.0

1.0

2.0

1.0

2.0

1.0

2.0

ns

2

4

SYSCLK duty

cycle measured

at 1.4 V

40

60

40

60

40

60

40

60

40

60

%

3

SYSCLK jitter

—

±150

—

±150

—

±150

±150

±150

ps

4

604e internal

PLL-relock time

—

100

—

100

—

100

100

100

µs

3, 5

Notes:

1. Caution: The SYSCLK frequency and PLL_CFG[0–3] settings must be chosen such that the resulting

SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective

maximum or minimum operating frequencies. Refer to the PLL_CFG[0–3] signal description in Section 1.8,

“System Design Information,” for valid PLL_CFG[0–3] settings.

2. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.

3. Timing is guaranteed by design and characterization, and is not tested.

4. The total input jitter (short term and long term combined) must be under

±150 ps to guarantee the input and

output timing shown in Section 1.4.2.2, “Input AC Specifications” and Section 1.4.2.3, “Output AC

Specifications.”

5. PLL-relock time is the maximum time required for PLL lock after a stable Vdd, OVdd, AVdd, and SYSCLK

are reached during the power-on reset sequence. Also note that HRESET must be held asserted for a

minimum of 255 bus clocks after the PLL-relock time (100

µs) during the power-on reset sequence.

6. AC timing specifications are tested up to the maximum SYSCLK frequency shown here. However, it is

theoretically possible to attain higher SYSCLK frequencies, if allowed for by system design or by using 604e

Fast Out mode (see Table 11 for details).

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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