PID9v-604e Hardware Specifications

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PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Figure 2 provides the input timing diagram for the 604e.

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Figure 2. Input Timing Diagram

Figure 3 provides the mode select input timing diagram for the 604e.

Figure 3. Mode Select Input Timing Diagram

1.4.2.3 Output AC Specifications

The output specifications of the 604e for both driving high and driving low depend on the capacitive loading

on each output and the drive capability enabled for that output. Additionally, the timing specifications for

outputs driving low also depend on the voltage swing required to drive to 0.8 V (either 5.5 V to 0.8 V or

3.6 V to 0.8 V). Table 8 provides the output AC timing specifications for a 50 pF load. In order to derive the

actual timing specifications for a given set of conditions, it is recommended that IBIS simulation models be

used. Contact the local Motorola or IBM sales office for information on the availability of these models.

The 604e adds a Fast Out output mode which will allow for increased system bus frequencies. Table 8

provides the output AC timing specifications for the 604e (shown in Figure 4) operating in 604

Compatibility mode and Fast Out mode. 604e Fast Out mode is selected by driving the L2_TSTCLK pin to

GND during assertion of HRESET. When Fast Out mode is enabled, the output valid and output hold times

are reduced.

VM

SYSCLK

ALL INPUTS

VM = Midpoint Voltage (1.4 V)

7

8

DRTRY

HRESET

VM

VM = Midpoint Voltage (1.4 V)

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Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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