PID9v-604e Hardware Specifications

5

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

— No-DRTRY mode eliminates the DRTRY signal from the qualified bus grant and allows read

operations. This improves performance on read operations for systems that do not use the

DRTRY signal. No-DRTRY mode makes read data available to the processor one bus clock

cycle sooner than if normal mode is used.

•

Multiprocessing support features include the following:

— Hardware enforced, four-state cache coherency protocol (MESI) for data cache. Bits are

provided in the instruction cache to indicate only whether a cache block is valid or invalid.

— Separate port into data cache tags for bus snooping

— Load/store with reservation instruction pair for atomic memory references, semaphores, and

other multiprocessor operations

•

Power management

— DOZE mode suspends instruction execution while allowing cache snooping

— NAP mode suspends all internal clocks except those required for decrementer, time base, and

interrupt logic

— Operating voltage of 2.5

± 0.125 V

•

Performance monitor can be used to help in debugging system designs and improving software

efficiency, especially in multiprocessor systems.

•

In-system testability and debugging features through JTAG boundary-scan capability

1.3 General Parameters

The following list provides a summary of the general parameters of the 604e:

Technology

0.35

µm CMOS, five-layer metal

Die size

12.9 mm x 11.7 mm (148 mm2)

Transistor count

5.1 million

Logic design

Fully-static

Package

255-lead ceramic ball grid array (CBGA)

Core power supply

2.5 V

± 5% V dc

I/O power supply

3.3 V

± 5% V dc

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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