VR5510 datasheet(17/203 Pages) NXP

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NXP Semiconductors

VR5510

Multi-output PMIC with SMPS and LDO

HVLDO regulator assigned to a slot using HVLDOS_OTP [2:0]

BOOST regulator assigned to a slot using BOOSTS_OTP [2:0]

The width of each slot is configurable via OTP using the SLOT_WIDTH_OTP [1:0] bitfield

SLOT_WIDTH_OTP [1:0] = 00 (Default) corresponds to 250 μs slot width

SLOT_WIDTH_OTP [1:0] = 01 corresponds to 500 μs slot width

SLOT_WIDTH_OTP [1:0] = 10 corresponds to 1000 μs slot width

SLOT_WIDTH_OTP [1:0] = 11 corresponds to 2000 μs slot width

aaa-039359

VSUP1,2

VSUP > VSUP_uvh

PWRON1VIH

VBOSUVH

tslot

1 ms max

with LBIST disabled

PWRON1

VBOS

VPRE

VPRE_UVH

SLOT_0

SLOT_1

SLOT_2

SLOT_6

PGOOD

RSTB

Figure 7. Typical start up diagram

The real power-up sequence depends not only on the slot OTP setting but also on the different soft-start times

for each regulator. If the LBIST is enabled, VBOSUVH to SLOT_0 timing can be higher than 1 ms. LBIST typical

duration is 3 ms.

8.12 Entering Debug mode using the VDDOTP pin

The VR5510 provides a means of evaluating the device in Debug mode. Debug mode allows users, via the I2C

interface, to access the OTP register set, modify the registers, and test device functions. During Debug mode all

regulators remain off.

The VR5510 enters in Debug mode with the following sequence:

1. Apply VDDOTP pin = VDDOTP.

2. Apply VSUP1/2 > VSUP_UVH and PWRON1 > PWRON1VIH or PWRON2 > PWRON2VIH.

3. The device now starts in Debug mode, ready for debugging or OTP programming.

4. Apply VDDOTP = 0 V to turn on the device with the modified configuration.

VR5510

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 31 July 2023

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