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VR5510 Datasheet(PDF) 65 Page - NXP Semiconductors

Part # VR5510
Description  Multi-output PMIC with SMPS and LDO
PDF  203 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

VR5510 Datasheet(HTML) 65 Page - NXP Semiconductors

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NXP Semiconductors
VR5510
Multi-output PMIC with SMPS and LDO
22 Safety
22.1 Functional description
The Fail-safe domain is electrically independent and physically isolated. The Fail-safe domain is supplied by
its own reference voltages and current, has its own oscillator, has a duplicate analog path to minimize common
cause failures, and has LBIST/ABIST to cover latent faults. The Fail-safe domain offers QM, ASIL B or ASIL
D compliancy depending on device part number. Fail-safe timings are derived from the Fail-safe oscillator with
±10% accuracy, unless otherwise specified.
The Fail-Safe domain and its dedicated pins are shown in Figure 29.
aaa-039389
OTP
Fail-Safe State Machine
ABIST
LBIST
Watchdog
MCU Failure
Monitoring
(FCCU)
STBY
PGOOD
Driver
Reset
Driver
Fail Safe
Output Driver
Voltage
Supervision
VDDIO
HVLDO
Vdig_FS
Vana_FS
VCOREMON
FCCU1/WDI
STBY
PGOOD
RSTB
FS0B
FCCU2
OSC
FS
I2C
FS
VMON1
VMON2
VMON3
VMON4 BG2
Vdig_FS
Figure 29. Fail Safe block diagram
Note: Refer to the VR5510 Device Guideline for more details on the schematic.
22.2 QM versus ASIL-B versus ASIL-D
Safety Features
QM
ASIL B
ASIL D
PGOOD output pin
Yes
Yes
Yes
RSTB output pin
Yes
Yes
Yes
FS0B output pin
No
Yes
Yes
Watchdog monitoring
No
Simple WD
Challenger WD
FCCU monitoring
No
Yes
Yes
MCU Fault Recovery Strategy
No
No
Yes
Analog BIST (ABIST)
No
Yes
Yes
Logical BIST (LBIST)
No
No
Yes
Table 44. QM VS ASIL-B VS ASIL-D safety features
VR5510
All information provided in this document is subject to legal disclaimers.
© 2023 NXP B.V. All rights reserved.
Product data sheet
Rev. 6 — 31 July 2023
65 / 203



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