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VR5510 Datasheet(PDF) 12 Page - NXP Semiconductors |
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VR5510 Datasheet(HTML) 12 Page - NXP Semiconductors |
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12 / 203 page  NXP Semiconductors VR5510 Multi-output PMIC with SMPS and LDO • VSUP minimum voltage depends on the external components (LPI_DCR) and the application conditions (IPRE, F_VPRESW). When VPRE is switching at 455 kHz, the VR5510 maximum continuous operating voltage is 36 V. The part is validated at 48 V for a limited duration of 15 minutes at room temperature to satisfy the jump-start requirement of 24 V applications. It can sustain a 58 V load dump without external protection. When VPRE is switching at 2.2 MHz, the VR5510 maximum continuous operating voltage is 18 V. The part is validated at 26 V for limited duration of 2 minutes at room temperature to satisfy the jump-start requirement of 12 V applications and a 35 V load dump. 8.4 Thermal ratings Symbol Parameter Conditions Min Max Unit RθJA Thermal Resistance Junction to Ambient [1] 2s2p circuit board [2] — 27 °C/W RθJA Thermal Resistance Junction to Ambient [1] 2s8p circuit board [2] — 17 °C/W RθJB Junction to Board Thermal Resistance 2s2p circuit board [2] — 22 °C/W RθJB Junction to Board Thermal Resistance 2s8p circuit board [2] — 15 °C/W RθJC_BOTTOM Junction to Case Bottom Thermal Resistance 2s8p and 2s2p circuit board [2] — 1.5 °C/W RθJC_TOP Junction to Case Top Thermal Resistance 2s8p and 2s2p circuit board [2] — 17 °C/W ΨJT_TOP Thermal Resistance Parameter Junction to top [1] Between the package top and the junction temperature [1] — 1 °C/W TA Ambient Temperature (Automotive) -40 125 °C TA Ambient Temperature (Industrial) -40 105 °C TJ Junction Temperature -40 150 °C TSTG Storage Temperature -55 150 °C Table 5. Thermal ratings [1] Determined in accordance with JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is solely for a thermal performance comparison of one package to another in a standardized specified environment. It is not meant to predict the performance of a package in an application-specific environment. Uniform power is assumed on die top surface. [2] Thermal test board meets JEDEC specification for this package (JESD51-9) 8.5 EMC compliancy Pin Pin_Type EMC Compliance VBAT (VSUP1/2) Global HV_HVLDO_IN Global PWRON1 Global Conducted Emissions – IEC 61967-4 (150 Ω method, 12-M level, 50% load on regulators) Conducted Immunity – IEC 62132-4 (36dBm, Class A, No state change on FS0B, RSTB, PGOOD, INTB, 50% load on all regulators and accuracy in spec FS0B Global Conducted Emissions – IEC 61967-4 (150 Ω method, 12-M level, 50% load on regulators) Conducted Immunity – IEC 62132-4 (30dBm, Class A, No state change on FS0B, RSTB, PGOOD, INTB, 50% load on all regulators and accuracy in spec Table 6. VR5510 EMC compliancy chart VR5510 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 31 July 2023 12 / 203 |
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