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VR5510 Datasheet(PDF) 13 Page - NXP Semiconductors |
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VR5510 Datasheet(HTML) 13 Page - NXP Semiconductors |
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13 / 203 page ![]() NXP Semiconductors VR5510 Multi-output PMIC with SMPS and LDO Pin Pin_Type EMC Compliance BUCK1/2/3_IN Local, Supply LDO1/2/3_IN Local, Supply LV_HVLDO_IN Local, Supply Conducted Emissions – IEC 61967-4 (150 Ω method, 10-K level, 50% load on regulators) Conducted Immunity – IEC 62132-4 (12dBm, Class A, HVLDO in switch mode. No state change on FS0B, RSTB, PGOOD, INTB, 50% load on all regulators and accuracy in spec VRE_FB Local BUCK1/2/3_FB Local LDO1/2/3 Local HVLDO Local VBOOST Local VBOS Local Conducted Emissions – IEC 61967-4 (150 Ω method, 10-K level, 50% load on regulators) Conducted Immunity – IEC 62132-4 (12 dBm, Class A. No state change on FS0B, RSTB, PGOOD, INTB, 50% load on all regulators and accuracy in spec PWRON2 Local Conducted Emissions – IEC 61967-4 (150 Ω method, 12-M level, 50% load on regulators) Conducted Immunity – IEC 62132-4 (12 dBm, Class A. No state change on FS0B, RSTB, PGOOD, INTB, 50% load on all regulators and accuracy in spec PGOOD Local RSTB Local STBY Local STBY_PGOOD Local VDDIO Local Conducted Emissions – IEC 61967-4 (150 Ω method, 10-K level, 50% load on regulators) Conducted Immunity – IEC 62132-4 (12 dBm, Class A. No state change on FS0B, RSTB, PGOOD, INTB, 50% load on all regulators and accuracy in spec Table 6. VR5510 EMC compliancy chart...continued VR5510 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 31 July 2023 13 / 203 |
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