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VR5510 Datasheet(PDF) 2 Page - NXP Semiconductors |
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VR5510 Datasheet(HTML) 2 Page - NXP Semiconductors |
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2 / 203 page  NXP Semiconductors VR5510 Multi-output PMIC with SMPS and LDO 2 Simplified application diagram aaa-039353 VBAT VR5510 BUCK1 BUCK2 BUCK3 LDO2 LDO1 I2C AMUX CLK Mgt (FSYNC) VPRE MCU WAKE PWRON1 PWRON2 Analog and digital monitoring BOOST FAIL SAFE STATE MACHINE VDD_CORE PCie VDD_DDR_IO VDD_3P3 LDO3 1P8_DDR HVLDO BUCK1 VDD_CORE_STBY VDD_3P3_LP To CAN PHY PGOOD, RSTB INTB STBY_PGOOD FIN FS0B FCCU1/2 STBY Figure 1. VR5510 simplified application diagram VR5510 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 31 July 2023 2 / 203 |
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