VR5510 datasheet(90/203 Pages) NXP

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NXP Semiconductors

VR5510

Multi-output PMIC with SMPS and LDO

VCORE_ABIST2

VCOREMON BIST executed during ABIST2

HVLDO_VMON_ABIST2

HVLDO VMON BIST executed during ABIST2

0 (default)

No ABIST2

HVLDO VMON BIST executed during ABIST2

Reset condition

POR

Table 76. ABIST2 setting...continued

An RSTB_DELAY_OTP bit is available to add a 5 ms delay between the end of the ABIST1 and RSTB/PGOOD

release.

TA = –40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UVH to 36 V, unless otherwise specified. All

voltages referenced to ground

Symbol

Parameter

Min

Typ

Max

Unit

ABIST

ABIST1TDUR

ABIST1 duration

• MIN with no voltage monitoring assigned by OTP

• MAX with all voltage monitoring assigned by OTP

0.2

—

1.4

ABIST2TDUR

ABIST2 duration

• MIN with no voltage monitoring selected by I2C

• MAX with all voltage monitoring selected by I2C

0.2

—

1.4

Table 77. Electrical characteristics

VR5510

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Product data sheet

Rev. 6 — 31 July 2023

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