VR5510 datasheet(67/203 Pages) NXP

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NXP Semiconductors

VR5510

Multi-output PMIC with SMPS and LDO

WD_WINDOW[3:0]

Watchdog Window Period

0001

1.0 ms

0010

2.0 ms

0011 (default)

3.0 ms

0100

4.0 ms

0101

6.0 ms

0110

8.0 ms

0111

12 ms

1000

16 ms

1001

24 ms

1010

32 ms

1011

64 ms

1100

128 ms

1101

256 ms

1110

512 ms

1111

1024 ms

Reset condition

POR

Table 45. Watchdog window period configuration...continued

The duty cycle of the watchdog window is configurable from 31.25% to 68.75% with the WDW_DC [2:0] bits

(FS_WD_WINDOW register). The new duty cycle is effective after the next watchdog refresh.

WDW_DC [2:0]

CLOSED window

OPEN window

000

31.25%

68.75%

001

37.5%

62.5%

010 (default)

50%

011

62.5%

37.5%

100

68.75%

31.25%

Others

50%

Reset condition

POR

Table 46. Watchdog window duty cycle configuration

22.4.1 Simple watchdog

The Simple watchdog uses a unique seed. The MCU can send its own seed to the WD_SEED bit

field (FS_WD_SEED register) or it can use the default value 0x5AB2. This seed must be written in the

WD_ANSWER bit field (FS_WD_ANSWER register) during the OPEN watchdog window. When the result is

correct, the watchdog window is restarted. When the result is incorrect, the WD error counter is incremented

and the watchdog window is restarted. In Simple watchdog configuration, a 0xFFFF and 0x0000 value cannot

be written to WD_SEED. If a 0x0000 or 0xFFFF write is attempted, a communication error is reported.

VR5510

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Product data sheet

Rev. 6 — 31 July 2023

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