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UDG−03042

Temperature

Compensation

Self−Discharge

Timer

Discharge

Current

Charge

Current

LastMeasured

Discharge(LMD)

Nominal Available

Charge(NAC)

Qualified

Transfer

LearningCount

Register(LCR)

Temperature,V oltage,

AverageCurrent,

OtherData

Compensated

AvailableCharge

+

+

_

_

INPUTS

COMPUTATIONS

OUTPUTS

Rate, Age,and

Temperature

Compensation

+

_

bq27010, bq27210

SLUS707B – APRIL 2006 – REVISED JANUARY 2007

FUNCTIONAL DESCRIPTION (continued)

When the battery is charged to full (NAC = LMD), the valid discharge flag (VDQ) bit in FLAGS will be set. It will

remain set during the subsequent discharge until the learning discharge cycle completes or an event occurs that

disqualifies the learning cycle. When the battery is discharged to the condition where VOLT

≤ EDV1 threshold,

the learning cycle will terminate and LMD will be updated if VDQ is still set. The bqJUNIOR EDV detection is

designed to prevent premature detection of the EDV threshold due to dynamic load variations. EDV detection

has a dynamically adjusted delay of up to 21.5 seconds with CSOC

≥ 6% and down to 3 seconds when CSOC =

0%. To prevent a severe reduction in LMD due to some abnormal situation, the new LMD value is restricted to a

learn-down maximum of DC/8 during any single learning cycle. When the learning cycle completes, LMD is

updated and the capacity inaccurate (CI) bit in FLAGS is cleared. The CI bit will remain cleared unless there is a

full reset (reset with RAM corruption detected) or the cycle count since the last learning cycle (CYCL) reaches a

count of 32.

A learning cycle can be disqualified by any of the following conditions:

1. Cold temperature: Temperature < 0

°C when the EDV1 threshold voltage is reached.

2. Light load: A capacity learning cycle is disqualified if average current is less than or equal to 2 times the

initial standby load when the EDV1 threshold voltage is reached.

3. Excessive charging: Cumulative Charge > 255 NAC counts (910 µVh) during a learning discharge cycle

(alternating discharge/charge/discharge before EDV1 is set).

4. Reset: VDQ is cleared on all resets.

5. Excessive self-discharge: NAC reduction from self-discharge estimate (0.195%) performed 64 times.

6. Self-discharge at termination of learning cycle. If self-discharge estimate causes CAC

≤ DC/16, VDQ is

cleared.

NAC is adjusted by charge and discharge coulometric measurements except when battery full or empty

conditions are detected. NAC = LMD is forced when IMIN = 1 (full detection) unless Temperature

≤

TCOMP[2:0]*2 (

°C). During a discharge with VDQ = 1, CAC is not allowed to drop below DC/16 until EDV1 = 1.

If EDV1 = 1 occurs when CAC > DC/16, CAC = DC/16 will be forced. CAC = 0 is forced if EDVF = 1.

Figure 4. Operational Overview

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