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Reported Battery Voltage Registers (VOLTL/VOLTH) — Address 0x08/0x09

Status Flag Register (FLAGS) — Address 0x0A

Relative State-of-Charge (RSOC) — Address 0x0B

bq27010, bq27210

SLUS707B – APRIL 2006 – REVISED JANUARY 2007

The VOLTH and the VOLTL low-byte registers contain the reported battery voltage measured on the BAT pin.

Voltage is expressed in mV with an LSB resolution of 1 mV. Reported voltage cannot exceed 5000 mV. The

host system has read-only access to this register pair. Voltage is updated every 2.56 seconds.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

NAME

CHGS

NOACT

IMIN

CI

CALIP

VDQ

EDV1

EDVF

POR STATUS

0

0

0

1

0

0

0

0

CHGS

Charge State flag. A 1 in the CHGS indicates a charge current (V

of charge activity. This bit should be read when the host system reads the Average Current

register pair to determine the sign of the average current magnitude. This bit is cleared to 0 on all

resets.

NOACT

No Activity flag. A 1 indicates that the voltage across R

See the Digital Magnitude Filter section for more information. This bit is cleared to 0 on all resets.

IMIN

Li-ion taper current detection flag. A 1 indicates that the charge current has tapered to less than

the value set in EEPROM and that the battery voltage is greater than or equal to the value

selected by the QV0 and QV1 bits in the PKCFG register (see EEPROM Data Register description

for more details). Taper current detection is disqualified if AI < 8 (28.6 µV across sense resistor).

The taper detection conditions must be maintained for 4 successive average current

measurements (20-25 s) to qualify as a valid taper current detection. This bit is cleared to 0 on all

resets.

CI

Capacity Inaccurate flag. A 1 indicates that the firmware has not been through a valid learning

cycle and is basing all calculations on initial design values programmed into EEPROM or that there

have been at least 32 cycle-count increments since the last learning cycle. This bit is cleared only

on a LMD update following a learning cycle. This bit is set to 1 on a full reset. The previous value

is retained if no RAM corruption is detected after a reset.

CALIP

Calibration-In-Progress flag. This flag is set whenever an automatic or commanded offset

calibration measurement is being made. This bit is set to 0 on all resets.

VDQ

Valid Discharge flag. A 1 indicates that the bqJUNIOR has met all necessary requirements for the

firmware to learn the battery capacity. This bit clears to 0 on a LMD update or condition that

disqualifies a learning cycle. This bit is cleared to 0 on all resets.

EDV1

First End-of-Discharge-Voltage flag. A 1 indicates that the voltage on the BAT pin is less than or

equal to the EDV1 threshold voltage. LMD updates immediately if the VDQ bit is set when this bit

transitions from 0 to 1. This bit is cleared when charging and on all resets.

EDVF

Final End-of-Discharge-Voltage flag. A 1 indicates that the voltage on the BAT pin is less than or

equal to the EDVF threshold voltage. This bit is cleared when charging and on all resets.

The host system has read-only access to this register.

RSOC reports the nominal available capacity as a percentage of the last measured discharge value (LMD). The

equation is:

RSOC (%) = 100 * NAC/LMD

The host system has read-only access to this register.

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