TAS5036B datasheet(36/56 Pages) TI

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System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes

SLES073—February 2003

TAS5036B

System Procedures for Initialization, Changing Data Rates, and

Switching Between Master and Slave Modes

4.1

System Initialization

Reset is used during system initialization to hold the TAS5036B inactive while power (VDD), the master clock

(MCLK_IN), the device control, and the data signals become stable. The recommended initialization

sequence is to hold RESET low for 24 MCLK_IN cycles after VDD has reached 3 V and the other control

signals (MUTE, PDN, M_S, ERR_RCVRY, DBSPD, and CS0) are stable.

Figure 4–1 shows the recommended sequence and timing for the RESET terminal duing system VDD voltage

and MCLK.

MCLK

VDD

3 V

24 MCLK_IN

Cycles

RESET

Figure 4–1. RESET During System Initialization

Within the first 2 ms following the low-to-high transition of the RESET terminal, the serial data interface format

should be set in the serial data interface control register using the I2C serial control interface. If the data rate

setting is other than the setting specificed by the DBSPD terminal, then the data rate should be set using the

DBSPD terminal or I2C interface within 2 ms. following the low-to-high transition of the RESET terminal.

The time available to set the I2C registers following the low-to-high transition of the RESET terminal can be

extended using the ERR_RCVRY terminal. While ERR_RCVRY is low, the TAS5036B outputs are held

inactive. Once the I2C control registers are set, the ERR_RCVRY terminal can be released and the TAS5036B

starts operation. Figure 4–2 shows how the ERR_RCVRY terminal can be used to extend the interval as long

as necessary to set the I2C registers following the low-to-high transition of the RESET terminal.

TAS5036B Datasheet(PDF) 36 Page - Texas Instruments