TAS5036B datasheet(40/56 Pages) TI

40 / 56 page

System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes

SLES073—February 2003

TAS5036B

MCLK

MUTE

Terminal

ERR_RCVRY

Terminal

Change from a 96-kHz data rate

MCLK_IN = 24.576 MHz

Clock unstable during transition.

HIGH and LOW intervals < 20 ns

Change to a 48-kHz data rate

MCLK_IN = 12.288 MHz

Volume Ramp

Up 120 ms

Volume Ramp

Down 60 ms

ERR_RCVRY can be set at

any time within this interval

Wait a minimum of 100

µs after the

LOW to HIGH transistion of RESET

Release ERR_RCVRY and

then MUTE when I2C

registers are programmed

> 5 ms

RESET

Terminal

< 2 ms

Set data rate and

restore other

via I2C

Figure 4–6. Changing the Data Sample Rate With An Unstable MCLK_IN Using the I2C

4.3

Changing Between Master and Slave Modes

The master and slave mode is set while the RESET terminal is active. Because this sequence employs the

RESET terminal the internal register settings are set to the default values.

Figure 4–7 shows the procedure to switch between master and slave modes and then restore the register

settings. In this example, the ERR_RCVRY terminal is used to hold off system re-initialization after RESET

is released. This permits the system controller to have as much additional time as necessary to restore the

Once the data rate is set, the ERR_RCVRY and MUTE terminal signals are set high and the system

re-initializes.

TAS5036B Datasheet(PDF) 40 Page - Texas Instruments

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