TAS5036B datasheet(31/56 Pages) TI

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Serial Control Interface Register Definitions

SLES073—February 2003

TAS5036B

Serial Control Interface Register Definitions

Table 3–1 shows the register map for the TAS5036B. Default values in this section are in bold.

Table 3–1. I2C Register Map

ADDR HEX

DESCRIPTION

General status register

Error status register

System control register 0

System control register 1

Error recovery register

Automute delay

DC-offset control register channel 1

DC-offset control register channel 2

DC-offset control register channel 3

DC-offset control register channel 4

DC-offset control register channel 5

DC-offset control register channel 6

Interchannel delay register channel 1

Interchannel delay register channel 2

Interchannel delay register channel 3

Interchannel delay register channel 4

Interchannel delay register channel 5

Interchannel delay register channel 6

ABD delay register

Volume control register channel 1

Volume control register channel 2

Volume control register channel 3

Volume control register channel 4

Volume control register channel 5

Volume control register channel 6

Individual channel mute

The volume table is contained in Appendix A.

Default values are shown in bold in the following tables.

TAS5036B Datasheet(PDF) 31 Page - Texas Instruments