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TAS5036B Datasheet(PDF) 48 Page - Texas Instruments |
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TAS5036B Datasheet(HTML) 48 Page - Texas Instruments |
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48 / 56 page ![]() Specifications 42 SLES073—February 2003 TAS5036B tsu(LRCLK) SCLK LRCLK NOTE: Serial data is sampled with the rising edge of SCLK (setup time = 20 ns and hold time = 10 ns). Figure 5–7. Right, Left, and IIS Serial Mode Timing Requirement LRCLK SCLK MCLK t(MRLD) t(MSD) Figure 5–8. Serial Audio Ports Master Mode Timing LRCLK SCLK SDIN tsu(LRCLK) th(LRCLK) tw(FSHIGH) tsu(SDIN) th(SDIN) Figure 5–9. DSP Serial Port Timing |
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