TAS5036B datasheet(14/56 Pages) TI

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Architecture Overview

SLES073—February 2003

TAS5036B

2.1.3.1

Crystal Type and Circuit

In clock master mode the TAS5036B can derive the MCLKOUT, SCLK, and LRCLK from a crystal. In this case,

the TAS5036B uses a parallel-mode fundamental-mode crystal. This crystal is connected to the TAS5036B

as shown in Figure 2–1.

TAS5036B

OSC

MACRO

AVSS

rd = Drive level control resistor – crystal vendor specified

CL = Crystal load capacitance (capacitance of circuitry between the two terminals of the crystal)

CL = (C1 x C2 )/(C1 + C2 ) + CS (where CS = board stray capacitance ~ 3 pF)

Example: Vendor recommended CL = 18 pF, CS = 3 pF ≥ C1 = C2 = 2 x (18–3) = 30 pF

Figure 2–1. Crystal Circuit

2.1.4 Clock Slave Mode

In the slave mode (M_S = 0), the master clock, LRCLK, and SCLK are inputs to the TAS5036B. The master

clock is supplied through the MCLK_IN terminal.

As in the master mode, the TAS5036B device develops its internal timing from the internal phase-locked loop

(PLL). The reference clock for the PLL is provided by the input to the MCLK_IN terminal. This input is at a

frequency of 256 times (128 in quad mode) the input data rate. The SCLK frequency is 48 or 64 times the data

sample rate. The LRCLK frequency is the data sample rate. The TAS5036B does not require any specific

phase relationship between SRCLK and MCLK_IN, but there must be synchronization. The TAS5036B

monitors the relationship between MCLK, SCLK, and LRCLK. The TAS5036B detects if any of the three clocks

are absent, if the LRCLK rate changes more than 10 MCLK cycles since the last device reset or clock error,

or if the MCLK frequency is changing substantially with respect to the PLL frequency.

When a clock error is detected, the TAS5036B performs a clock error management sequence.

The clock error management sequence temporarily suspends processing, places the PWM outputs in a hard

mute (PWM_P outputs are low; PWM_M outputs are high, and all VALID signals are low), resets all internal

processes, sets the volumes to mute, and suspends all I2C operations.

When the error condition is corrected, the TAS5036B exits the clock error sequence by performing a partial

re-initialization, noiselessly restarting the PWM output, and ramping the volume up to the level specified in

the volume control registers. This sequence is performed over a 60 ms. interval. The TAS5036B preserves

all control register settings that were set prior to the clock interruption.

If a clock error occurs while the ERR_RCVRY terminal is asserted (low), the TAS5036B performs the error

management sequence up to the unmute sequence. In this case, the volume remains at full attenuation with

the PWM output at a 50% duty cycle. The volume can be restored from this latched mute state by triggering

a mute/unmute sequence by asserting and releasing MUTE either by using the terminal, the system control

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