TAS5036B datasheet(30/56 Pages) TI

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Architecture Overview

SLES073—February 2003

TAS5036B

D0 ACK

Stop

Condition

Acknowledge

I2C Device Address and

Read/Write Bit

Last Data Byte

R/W ACK A7

ACK D7

D0 ACK

Start Condition

Acknowledge

First Data Byte

Other

Data Bytes

Figure 2–15. Multiple Byte Write Transfer

2.5.3 Single Byte Read

As shown in Figure 2–16, a single byte data read transfer begins with the master device transmitting a start

condition followed by the I2C device address and the read/write bit. For the data read transfer, a write followed

by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory

address to be read. As a result, the read/write bit is 0. After receiving the TAS5036B address and the read/write

bit, the TAS5036B responds with an acknowledge bit. Also, after sending the internal memory address byte

or bytes, the master device transmits another start condition followed by the TAS5036B address and the

read/write bit again. This time the read/write bit is a 1 indicating a read transfer. After receiving the TAS5036B

and the read/write bit, the TAS5036B again responds with an acknowledge bit. Next, the TAS5036B transmits

the data byte from the memory address being read. After receiving the data byte, the master device transmits

a not acknowledge followed by a stop condition to complete the single byte data read transfer.

A0 R/W ACK A7

A0 ACK

ACK

Start

Condition

Stop

Condition

Acknowledge

I2C Device Address and

Read/Write Bit

Data Byte

D0 ACK

I2C Device Address and

Read/Write Bit

Repeat Start Condition

Not

Acknowledge

R/W

Figure 2–16. Single Byte Read

2.5.4 Multiple Byte Read

A multiple byte data read transfer is identical to a single byte data read transfer except that multiple data bytes

are transmitted by the TAS5036B to the master device as shown in Figure 2–17. Except for the last data byte,

the master device responds with an acknowledge bit after receiving each data byte.

ACK

Acknowledge

I2C Device Address and

Read/Write Bit

R/W

A0 R/W ACK

ACK

D0 ACK

Start

Condition

Stop

Condition

Acknowledge

Last Data Byte

ACK

First Data Byte

Repeat Start

Condition

Not

Acknowledge

I2C Device Address and

Read/Write Bit

Other

Data Bytes

Figure 2–17. Multiple Byte Read

TAS5036B Datasheet(PDF) 30 Page - Texas Instruments

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