RT3662EB

Copyright © 2019 Richtek Technology Corporation. All rights reserved.

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

DS3662EB-04

August

2019

8

Table 3. SET1 Pin Setting for VDDC Controller QR Threshold

SET1 Pin Setting Voltage

UD

SET1_IR

UD

RR

V

80

μ

RR













QR Threshold

(GFX)

Min

Typical

Max

Unit

829.28

850

870.72

mV

Disable

1034.64

1050

1065.36

mV

20mV

1137.32

1150

1162.68

mV

25mV

Table 4. TSEN Pin Setting for VDDC Controller Frequency, Initial Offset and PHOCP Setting Ratio

TSEN Pin Setting Voltage

D

TSEN_DIV

UD

R

V

3.2

RR









 Frequency Initial Offset

PHOCP Setting

Ratio (Percentage

of OCP_SPIKE)

Min

Typical

Max

Unit

6.75

25

43.25

mV

300kHz

25mV

150%

57.25

75

92.75

mV

200%

208.75

225

241.25

mV

0mV

150%

259.25

275

290.75

mV

200%

410.75

425

439.25

mV

25mV

150%

461.25

475

488.75

mV

200%

612.75

625

637.25

mV

50mV

150%

663.25

675

686.75

mV

200%

814.75

825

835.25

mV

400kHz

25mV

150%

865.25

875

884.75

mV

200%

1016.75

1025

1033.25

mV

0mV

150%

1067.25

1075

1082.75

mV

200%

1218.75

1225

1231.25

mV

25mV

150%

1269.25

1275

1280.75

mV

200%

1420.75

1425

1429.25

mV

50mV

150%

1471.25

1475

1478.75

mV

200%

PHOCP_TH = OCP_SPIKE × (PHOCP Setting Ratio) / M

(M : Phase Number)