RT3662EB

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DS3662EB-04

August

2019

20

Power-Down Sequence

If the voltage at the EN pin falls below the enable falling

threshold, the controller is disabled. The voltage at the

PGOOD pin will immediately go low when EN pin signal

goes low, and the VDDC controller executes soft-

shutdown operation. The internal digital circuit ramps

down the reference voltage at the same slew rate as

that of in soft-start, making VDDC output voltage

gradually decrease in CCM. The Boot VID information

stored in the internal register is cleared at POR. This

event forces the RT3662EB to check the SVC and SVD

inputs for a new Boot VID when the EN voltage goes

high again.

PGOOD

The PGOOD is open-drain logic output. It provides the

power good signal when VDDC output voltage is within

the regulation limits and no protection is triggered. The

pin is typically tied to 3.3V or 5V power source through

a pull-high resistor. During shutdown state (EN = low)

and the soft-start period, the PGOOD voltage is pulled

low. After a successful soft-start and VDDC output

voltage is within the regulation limits, the PGOOD is

released high.

The voltage at the PGOOD pin will be pulled low when

any of the following events occurs : over-voltage

protection,

under-voltage

protection,

over-current

protection, and logic low EN voltage.

SVI2 Wire Protocol

The

RT3662EB

complies

with

AMD's

Voltage

Regulator Specification, which defines the Serial VID

Interface 2.0 (SVI2) protocol. With SVI2 protocol, the

processor directly controls the reference voltage level

of each individual controller channel and determines

which controller operates in power saving mode. The

SVI2 interface is a three-wire bus that connects a

single master to one or above slaves. The master

initiates and terminates SVI2 transactions and drives

the clock, SVC, and the data, SVD, during a transaction.

The

slave

drives

the

telemetry,

SVT

during

a

transaction. The AMD processor is always the master.

The voltage regulator controller (RT3662EB) is always

the slave. The RT3662EB receives the SVID code and

acts accordingly. The SVI protocol supports 20MHz

high speed mode I2C, which is based on SVD data

packet. Table 6 shows the SVD data packet. A SVD

packet consists of a “Start” signal, three data bytes

after each byte, and a “Stop” signal. The 8-bit serial

VID codes are listed in Table1. After the RT3662EB

has received the stop sequence, it decodes the

received serial VID code and executes the command.

The controller has the ability to sample and report

voltage and current for the VDDC domains. The

controller reports this telemetry serially over the SVT

wire which is clocked by the processor driven SVC. A

bit TFN at SVD packet along with the VDDC domain

selector bits are used by the processor to change the

telemetry functionality. The telemetry bit definition is

listed in Figure 3. The detailed SVI2 specification is

outlined in the AMD Voltage Regulator and Voltage

Regulator Module (VRM) and Serial VID Interface 2.0

(SVI2) Specification.

Table 6. SVD Data Packet

Bit Time

Description

1 : 5

Always 11000b

6

VDDC domain selector bit, if set then the following two data bytes contain the VID, the PSI

state, and the load-line slope trim and offset trim state for VDDC.

8

Always 0b

10

PSI0_L

11 : 17

VID Code bits [7:1]

19

VID Code bit [0]

20

PSI1_L