RT3662EB datasheet(22/28 Pages) RICHTEK

22 / 28 page

RT3662EB

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

DS3662EB-04

August

2019

Table 7. VDDC VR Power State

Full Phase

Number

PSI0_L : PSI1_L

Mode

2 phase CCM

1 phase DEM

1 phase CCM

1 phase DEM

Differential Remote Sense Setting

The VDDC controller has differential remote-sense

inputs to eliminate the effects of voltage drops along the

PC board traces, processor internal power routes and

socket contacts. The processor contains on-die sense

pins, including of VDDC_SENSE, and VSS_SENSE.

For VDDC controller, connect FB to VDDC_SENSE with

a resistor to build the negative input path of the error

amplifier, and connect VSS_SENSE to RGND as shown

in Figure 4. The precision reference voltages refer to

RGND for accurate remote sensing.

VSS_SENSE

VDDC_SENSE

RGND

VDDC

Controller

Processor

Figure 4. Differential Remote Sense Connection

SET1 Pin Setting

The RT3662EB provides the SET1 pin for platform

users to set the VDDC controller current gain ratio

(AI_VDDC), QR threshold (QR_TH). Platform designers

should use resistive voltage divider on the pin, refer to

Figure 5. The voltage (VREF) at VREF_PINSET pin will

be pulled up to 3.2V for SET1 pin setting after power

ready (POR), and then the voltage will change and fix to

0.8V with a delay time for normal operation.

The divided voltage at the SET1 pin as below :

SET1_DIV

3.2





(1)

The ADC monitors and decodes the voltage at this pin

only once after power up. After ADC decoding (only

once), a 80

A current (when VCC = 5V) will be

generated at the SET1 pin for pin setting. That is the

voltage at SET1 pin described as below:

SET1_IR









(2)

From equation (1) and (2) and Table 2 and 3, platform

users can set the above described pin setting functions.

SET1

VREF

80µA

(VCC = 5V)

SET1

ADC

VSET1_DIV

AI_VDDC

QR_TH

VSET1_IR

Figure 5. SET1 Pin Setting

TSEN Pin Setting

The RT3662EB provides the TSEN pin for platform

users to set the pin setting functions, including the

VDDC controller switching frequency (Fsw), Initial offset

and

per-phase

over

current

protection (PHOCP).

Platform designers should use resistive voltage divider

on the pin, refer to Figure 6. The voltage (VREF) at

VREF_PINSET pin will be pulled up to 3.2V for TSEN

pin setting after power ready (POR), and then the

voltage will change and fix to 0.8V with a delay time for

normal operation.

The divided voltage at the TSEN pin described as

below :

TSEN DIV

3.2





(3)

The ADC monitors and decodes the voltage at this pin

only once after power up. After ADC decoding (only

once), a 80

A current (when VCC = 5V) will be

generated at the TSEN pin for thermal indicator and

protection functions.

From equation (3) and Table 4, platform users can set

the above described pin setting functions.

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