CDC906 datasheet(16/39 Pages) TI

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Functional Description of the Logic

CDC906

SCAS828 – SEPTEMBER 2006

All Bytes are read-/write-able, unless otherwise expressly mentioned.

Byte 0 (read only): Vendor Identification Bits [3:0]; Revision Code Bit [7:4]

Revision Code(1)

Vendor Identification

(1)

Byte 0 is readable by "Byte Read sequency" only.

Byte 1 to 9: Reference Divider M of PLL1, PLL2, PLL3(1)

Div by

Default(2)(3)

Not allowed

•

509

510

511

(1)

By selecting the PLL divider factors, M

≤ N and 80 MHz ≤ fvco ≤ 300 MHz.

(2)

Unless customer specific setting.

(3)

Default setting of divider M for PLL1 = 1, for PLL2 = 27 and for PLL3 = 375.

Byte 1 to 9: Feedback Divider N of PLL1, PLL2, PLL3(1)

N11

N10

Div by

Default(2)(3)

Not

allowed

•

4093

4094

4095

(1)

By selecting the PLL divider factors, M

≤ N and 80 MHz ≤ fvco ≤ 300 MHz.

(2)

Unless customer specific setting.

(3)

Default setting of divider N for PLL1 = 8, for PLL2 = 250 and for PLL3 = 3136.

Byte 3 Bit [7:5]: PLL (VCO) Bypass Multiplexer

PLLxMUX

PLL (VCO) MUX Output

Default(1)

PLLx

Yes

VCO bypass

(1)

Unless customer specific setting.

Byte 6 Bit [7:5]: VCO Frequency Selection Mode for each PLL(1)

PLLxFVCO

VCO Frequency Range

Default(2)

80-200 MHz

180-300 MHz

Yes

(1)

This bit selects the normal-speed mode or the high-speed mode for the dedicated VCO in PLL1, PLL2 or PLL3. At power-up, the

high-speed mode is selected, fVCO is 180-300 MHz. In case of higher fVCO, this bit has to be set to [1].

(2)

Unless customer specific setting.

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