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• Measured Y1: 48 MHz

• Y0 is 27 MHz (XTAL buffered ,loaded by 50O)

• Y2 is 56.448 MHz (loaded by 50O)

• Y3 is 33.33 MHz (loaded by 50O)

• Y4, Y5 tri−stated

carrier

48MHz

spur at

27MHz&54MHz

carrier

48MHz

carrier

48MHz

spurs at

47MHz&49MHz

carrier

48MHz

spurs at

47MHz&49MHz

spur 47MHz and

fundamental at 1MHz

w Measured Y0: 48 MHz

w Y1, Y2, Y3, Y4 & Y5 tri−stated

w Inserted 30mV 1MHz @ Vcc = 3.3V

Phase Noise Characteristic

CDC906

SCAS828 – SEPTEMBER 2006

Figure 31. Noise Coupling and Spur Suppression

Figure 32. Power Supply Noise Rejection

In high-speed communication systems, the phase noise characteristic of the PLL frequency synthesizer is of

high interest. Phase noise describes the stability of the clock signal in the frequency domain, similar to the jitter

specification in the time domain.

Phase noise is a result of random and discrete noise causing a broad slope and spurious peaks. The discrete

spurious components could be caused by known clock frequencies in the signal source, power line interference,

and mixer products. The broadening caused by random noise fluctuation is due to phase noise. It can be the

result of thermal noise, shot noise and/or flicker noise in active and passive devices.

Important factor for PLL synthesizer is the loop bandwidth (–3 dB cut-off frequency) — large loop bandwidth

(LBW) results in fast transient response but have less reference spur attenuation. The LBW of the CDC906 is

about 100 kHz to 250 kHz, dependent on selected PLL parameter.

For the CDC906, two phase noise characteristics are of interest: The phase noise of the crystal-input stage and

the phase noise of the internal PLL (VCO). Figure 33 shows the respective phase noise characteristic.

34

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