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T =25 C,

V

=3.3V,

A

CC

o

Mdiv=4,

Ndiv=15,

P div=3

High-Speed Mode

180MHz

f

FrequencyRange

VCO

forHigh-SpeedMode

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forNormal-SpeedMode

Normal-SpeedMode

200MHz

Cross Coupling, Spur Suppression, and Noise Rejection

CDC906

SCAS828 – SEPTEMBER 2006

The TI Pro Clock software automatically calculates the PLL parameter for jitter-optimized performance.

Cross-Coupling in ICs occurs through interactions between several parts of the chip such as between output

stages, metal lines, bond wires, substrate, etc. The coupling can be capacitive, inductive and resistive (ohmic)

induced by output switching, leakage current, ground bouncing, power supply transients, etc.

The CDC906 is designed in BiCMOS process technology incorporating silicon-germanium (SiGe) technology.

This process gives excellent performance in linearity, low power consumption, best-in-class noise performance

and good isolation characteristic between the on-chip components.

The good isolation was a major criteria to use BiCMOS process as it minimizes the coupling effect. Even if all

three PLLs are active and all outputs are on, the noise suppression is clearly above 50 dB. Figure 31 and

Figure 32 show an example of noise coupling, spur-suppression, and power supply noise rejection of CDC906.

Die respective measurement conditions are shown in Figure 31 and Figure 32.

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