DSP56004ROM datasheet(31/82 Pages) FREESCALE

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Specifications

RESET, Stop, Mode Select, and Interrupt Timing

MOTOROLA

DSP56004/D, Rev. 3

2-7

RESET, STOP, MODE SELECT, AND INTERRUPT TIMING

Table 2-7

Reset, Stop, Mode Select, and Interrupt Timing (CL = 50 pF + 2 TTL Loads)

No.

Characteristics

All frequencies

Unit

Min

Max

Minimum RESET assertion width:

•

PLL disabled

•

PLL enabled1

× T

2500

× ET

—

Mode Select Setup Time

—

Mode Select Hold Time

—

Minimum Edge-triggered Interrupt Request Assertion

Width

—

16a Minimum Edge-triggered Interrupt Request

Deassertation Width

—

18 Delay from IRQA, IRQB, NMI Assertion to GPIO Valid

Caused by First Interrupt Instruction Execution

× T

C + TH

—ns

Delay from General Purpose Output Valid to Interrupt

Request Deassertation for Level Sensitive Fast

Interrupts—If Second Interrupt Instruction is: 2

•

Single Cycle

•

Two Cycles

TL – 31

× T

C) + TL – 31

Duration of IRQA Assertion for Recovery from Stop State

—

Duration for Level Sensitive IRQA Assertion to ensure

interrupt service (when exiting “Stop”)

•

Stable External Clock, OMR Bit 6 = 1

•

Stable External Clock, PCTL Bit 17 = 1

× T

C + TL

—

Note:

This timing requirement is sensitive to the quality of the external PLL capacitor connected to the PCAP

pin. For capacitor values

≤ 2 nF, asserting RESET according to this timing requirement will ensure

proper processor initialization for capacitors with a

∆C/C < 0.5%. (This is typical for ceramic

capacitors.) For capacitor values > 2 nF, asserting RESET according to this timing requirement will

ensure proper processor initialization for capacitors with a

∆C/C < 0.01%. (This is typical for Teflon,

polystyrene, and polypropylene capacitors.) However, capacitors with values > 2 nF with a

∆C/C > 0.01% may require longer RESET assertion to ensure proper initialization.

When using fast interrupts and IRQA and IRQB are defined as level-sensitive, then timing 22 applies to

prevent multiple interrupt service. To avoid these timing restrictions, the Negative Edge-triggered

mode is recommended when using fast interrupts. Long interrupts are recommended when using

Level-sensitive mode.

Figure 2-2 Reset Timing

RESET

VIHR

AA0251

Freescale Semiconductor, Inc.

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