DSP56004ROM datasheet(42/82 Pages) FREESCALE

42 / 82 page

2-18

DSP56004/D, Rev. 3

MOTOROLA

Specifications

External Memory Interface (EMI) SRAM Timing

98 RD Deassertation to Data

Not Valid (Data Hold Time)

tOHZ

0—0—

—

99 Address Valid to WR

Deassertation

tCW, tAW 3 × TC + TL –14 +

× T

—

29.2

—

100 Data Setup Time to WR

Deassertation

tDS (tDW)TC + TL – 5 +

× T

—

11.0

—

101 Data Hold Time from WR

Deassertation

tDH

TH – 6

4—2—

0.2

—

102 WR Assertion to Data Valid

—

TH + 4

—

10.2

103 WR Deassertation to Data

high impedance1

—TH + 10

—

16.2

104 WR Assertion to Data

Active

—TH – 6

4—2—

0.2

—

Note:

This value is periodically sampled and not 100% tested.

Figure 2-13 SRAM Read Cycle

Table 2-10

External Memory Interface (EMI) SRAM Timing

No.

Characteristics

Symbol

Expression

50 MHz

66 MHz

81 MHz

Unit

Min Max Min Max Min Max

MA0–MA14

MA15/MCS3

MA16/MCS2/MCAS

MA17/MCS1/MRAS

MCS0

Data In

MD0–MD7

AA0267

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

DSP56004ROM Datasheet(PDF) 42 Page - Freescale Semiconductor, Inc

DSP56004ROM Datasheet(HTML) 42 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

Datasheet Download

Link URL