DSP56004ROM datasheet(34/82 Pages) FREESCALE

34 / 82 page

2-10

DSP56004/D, Rev. 3

MOTOROLA

Specifications

External Memory Interface (EMI) DRAM Timing

54 CAS Deassertation Pulse

Width

(Page Mode Access

Only)

tCP

TC – 5

—

7.3

—

55 Row Address Valid to

RAS Assertion

(Row Address Setup

Time)

tASR

TL – 6

4—2—

0.2

—

56 RAS Assertion to ROW

Address Not Valid

(Row Address Hold

Time)

tRAH

slow

fast

× T

C + TH –

× T

C + TH –

—

29.2

16.9

—

57 Column Address Valid

to CAS Assertion

(Column Address Setup

Time)

tASC

TL – 6

4—2—

0.2

—

58 CAS Assertion to

Column Address Not

Valid

(Column Address Hold

Time)

tCAH

slow

fast

× T

C + TH –

× T

C + TH –

—

29.2

16.9

—

59 Last CAS Assertion to

Column Address Not

Valid (Column Address

Hold Time)

tCAH

slow

fast

× T

C + TH –

4 × T

C + TH –

136

—

100

—

78.6

41.6

—

60 RAS Assertion to

Column Address Not

Valid

tAR

slow

fast

× T

C + TH –

× T

C + TH –

136

—

100

—

78.6

53.9

—

61 Column Address Valid

to RAS Deassertation

tRAL

slow

fast

× T

C + TL – 7

× T

C + TL – 7

—

36.2

23.9

—

62 CAS, RAS, RD, or WR

Deassertation to WR or

RD Assertion

tRCH,

tRRH

slow

fast

× T

C – 11

× T

C – 11

—

50.7

26.0

—

63 CAS or RD Deassertation

to Data Not Valid

(Data Hold Time)

tOFF, tGZ

0—0—

—

64 Random Read or Write

Cycle Time (Single

Access Only)

tRC

slow

fast

× T

240

160

—

182

121

—

148

98.8

—

Table 2-8

External Memory Interface (EMI) DRAM Timing (Continued)

No.

Characteristics

Symbol

Timing

Mode

Expression

50 MHz

66 MHz

81 MHz

Unit

Min Max Min Max Min Max

Freescale Semiconductor, Inc.

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