DSP56004ROM datasheet(50/82 Pages) FREESCALE

50 / 82 page

2-26

DSP56004/D, Rev. 3

MOTOROLA

Specifications

Serial Host Interface (SHI) SPI Protocol Timing

163 First SCK Edge to

HREQ In Not Asserted

(HREQ In Hold Time)

master

0—0—

—

Note:

For an Internal Clock frequency below 33 MHz, the minimum permissible Internal Clock to Serial Clock

frequency ratio is 4:1. For an Internal Clock frequency above 33 MHz, the minimum permissible Internal Clock

to Serial Clock frequency ratio is 6:1.

In CPHA = 1 mode, the SPI slave supports data transfers at tSPICC = 3 × TC, if the user assures that the HTX

is written at least TC ns before the first edge of SCK of each word.In CPHA = 1 mode, the SPI slave

supports data transfers at tSPICC = 3 × TC, if the user assures that the HTX is written at least TC ns before

the first edge of SCK of each word.

When CPHA = 1, the SS line may remain active low between successive transfers.

Periodically sampled, not 100% tested

Figure 2-17 SPI Master Timing (CPHA = 0)

Table 2-12

Serial Host Interface (SHI) SPI Protocol Timing (Continued)

No.

Characteristics

Mode

Filter

Mode

Expression

50 MHz

66 MHz

81 MHz

Unit

Min Max Min Max Min

Max

(Input)

SCK (CPOL = 0)

(Output)

SCK (CPOL = 1)

(Output)

MISO

(Input)

Valid

MOSI

(Output)

MSB

Valid

LSB

MSB

LSB

HREQ

(Input)

141

142

143

144

141

144

143

142

148

149

148

152

153

163

161

AA0271

Freescale Semiconductor, Inc.

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