DSP56004ROM datasheet(10/82 Pages) FREESCALE

10 / 82 page

1-4

DSP56004/D, Rev. 3

MOTOROLA

Signal/Connection Descriptions

Clock and PLL signals

CLOCK AND PLL SIGNALS

Note:

While the PLL on this DSP is identical to the PLL described in the DSP56000

Family Manual, two of the signals have not been implemented externally.

Specifically, there is no PLOCK signal or CKOUT signal available. Therefore,

the internal clock is not directly accessible and there is no external indication

that the PLL is locked. These signals were omitted to reduce the number of

pins and allow this DSP to be put in a smaller, less expensive package.

Table 1-4

Clock and PLL Signals

Signal

Name

Signal

Type

State

during

Reset

Signal Description

EXTAL

Input

External Clock/Crystal

—This input should be connected to an

external clock source. If the PLL is enabled, this signal is

internally connected to the on-chip PLL. The PLL can multiply

the frequency on the EXTAL pin to generate the internal DSP

clock. The PLL output is divided by two to produce a four-phase

instruction cycle clock, with the minimum instruction time being

two PLL output clock periods. If the PLL is disabled, EXTAL is

divided by two to produce the four-phase instruction cycle clock.

PCAP

Input

PLL Filter Capacitor

—This input is used to connect a high-

quality (high “Q” factor) external capacitor needed for the PLL

filter. The capacitor should be as close as possible to the DSP with

heavy, short traces connecting one terminal of the capacitor to

PCAP and the other terminal to VCCP. The required capacitor

value is specified in Table 2-6 on page 2-6.

Note:

When short lock time is critical, low dielectric absorption

capacitors such as polystyrene, polypropylene, or teflon are

recommended.

If the PLL is not used (i.e., it remains disabled at all times), there is

no need to connect a capacitor to the PCAP pin. It may remain

unconnected, or be tied to either Vcc or GND.

PINIT

Input

PLL Initialization (PINIT)

—During the assertion of hardware

reset, the value on the PINIT line is written into the PEN bit of the

PCTL register. When set, the PEN bit enables the PLL by causing

it to derive the internal clocks from the PLL voltage controlled

oscillator output. When the bit is cleared, the PLL is disabled and

the DSP’s internal clocks are derived from the clock connected to

the EXTAL signal. After hardware RESET is deasserted, the

PINIT signal is ignored.

Freescale Semiconductor, Inc.

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