DSP56004ROM datasheet(61/82 Pages) FREESCALE

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Specifications

On-Chip Emulation (OnCE

™) Timing

MOTOROLA

DSP56004/D, Rev. 3

2-37

ON-CHIP EMULATION (OnCE

™) TIMING

(CL = 50 pF + 2 TTL Loads)

Table 2-17

OnCE Timing

No.

Characteristics

All frequencies

Unit

Min

Max

230

DSCK Low

—

231

DSCK High

—

232

DSCK Cycle Time

200

—

233

DR Asserted to DSO (ACK) Asserted

5 TC

—ns

234

DSCK High to DSO Valid

—

235

DSCK High to DSO Invalid

—

236

DSI Valid to DSCK Low (Set-up)

—

237

DSCK Low to DSI Invalid (Hold)

—

238

Last DSCK Low to OS0–OS1, ACK Active

3 TC + TL

—ns

239

DSO (ACK) Asserted to First DSCK High

2 TC

—ns

240

DSO (ACK) Assertion Width

4 TC + TH – 3

5 TC + 7

241

DSO (ACK) Asserted to OS0–OS1 High

Impedance1

—0

242

OS0–OS1 Valid to EXTAL Transition #2

T C – 21

—

243

EXTAL Transition #2 to OS0–OS1 Invalid

—

244

Last DSCK Low of Read Register to First DSCK

High of Next Command

7 TC + 10

—

245

Last DSCK Low to DSO Invalid (Hold)

—

246

DR Assertion to EXTAL Transition #2 for Wake

Up from Wait State

TC – 10

247

EXTAL Transition #2 to DSO After Wake Up from

Wait State

17 TC

—ns

Freescale Semiconductor, Inc.

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