DSP56004ROM datasheet(35/82 Pages) FREESCALE

35 / 82 page

Specifications

External Memory Interface (EMI) DRAM Timing

MOTOROLA

DSP56004/D, Rev. 3

2-11

65 WR Deassertation to

CAS Assertion

tRCS

slow

fast

× T

C – 11

× T

C – 11

169

109

—

125

—

100

63.1

—

66 CAS Assertion to WR

Deassertation

tWCH

slow

fast

× T

C – 13

× T

C – 13

—

11.7

—

67 Data Valid to CAS

Assertion

(Data Setup Time)

tDS

TL – 6

4—2—

0.2

—

68 CAS Assertion to Data

Not Valid (Data Hold

Time)

tDH

slow

fast

× T

C + TH –

× T

C + TH –

—

29.2

16.8

—

69 RAS Assertion to Data

Not Valid

tDHR

slow

fast

× T

C + TH –

× T

C + TH –

136

—

100

—

78.6

53.9

—

70 WR Assertion to CAS

Assertion

tWCS

slow

fast

× T

C – 14

× T

C – 14

—

35.4

—

71 WR Assertion Pulse

Width (Single Cycle

Only)

tWP

slow

fast

× T

C – 9

× T

C – 9

131

—

77.4

52.7

—

72 RAS Assertion to WR

Deassertation

(Single Cycle Only)

tWCR

slow

fast

× T

C – 15

× T

C – 15

125

—

71.5

46.7

—

73 WR Assertion to Data

Active

slow

fast

× T

C + TH –

× T

C + TH –

—

30.2

17.9

—

74 RD or WR Assertion to

RAS Deassertation

(Single Cycle Only)

tROH,

tRWL

slow

fast

× T

C – 13

× T

C – 13

127

—

73.4

48.7

—

Note:

n is the number of successive accesses. n = 2, 3, 4, or 6.

Table 2-8

External Memory Interface (EMI) DRAM Timing (Continued)

No.

Characteristics

Symbol

Timing

Mode

Expression

50 MHz

66 MHz

81 MHz

Unit

Min Max Min Max Min Max

Freescale Semiconductor, Inc.

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