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DSP56004ROM Datasheet(PDF) 44 Page - Freescale Semiconductor, Inc |
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DSP56004ROM Datasheet(HTML) 44 Page - Freescale Semiconductor, Inc |
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44 / 82 page  2-20 DSP56004/D, Rev. 3 MOTOROLA Specifications Serial Audio Interface (SAI) Timing SERIAL AUDIO INTERFACE (SAI) TIMING (CL = 50 pF + 2 TTL Loads) Table 2-11 Serial Audio Interface (SAI) Timing No. Characteristics Mode Expression 50 MHz 66 MHz 81 MHz Unit Min Max Min Max Min Max 111 Minimum Serial Clock Cycle = tSAICC (min) master slave 4 × T C 3 × T C + 5 80 65 — — 61 51 — — 49.4 42 — — ns ns 112 Serial Clock High Period master slave 0.5 × t SAICC – 8 0.35 × t SAICC 32 23 — — 22 18 — — 16.7 14.7 — — ns ns 113 Serial Clock Low Period master slave 0.5 × t SAICC – 8 0.35 × t SAICC 32 23 — — 22 18 — — 16.7 14.7 — — ns ns 114 Serial Clock Rise/Fall Time master slave 8 0.15 × t SAICC — — 8 10 — — 8 8 — — 8 6.3 ns ns 115 Data In Valid to SCKR edge (Data In Set-up Time) master slave 26 4 26 4 — — 26 4 — — 26 4 — — ns ns 116 SCKR Edge to Data In Not Valid (Data In Hold Time) master slave 0 14 0 14 — — 0 14 — — 0 14 — — ns ns 117 SCKR Edge to Word Select Out Valid (WSR Out Delay Time) master 20 — 20 — 20 — 20 ns 118 Word Select In Valid to SCKR Edge (WSR In Set-up Time) slave 12 12 — 12 — 12 — ns 119 SCKR Edge to Word Select In Not Valid (WSR In Hold Time) slave 12 12 — 12 — 12 — ns 121 SCKT Edge to Data Out Valid (Data Out Delay Time) master slave1 slave2 13 40 TH + 34 — — — 13 40 44 — — — 13 40 41 — — — 13 40 40.2 ns ns ns 122 SCKT Edge to Word Select Out Valid (WST Out Delay Time) master 19 — 19 — 19 — 19 ns 123 Word Select In Valid to SCKT Edge (WST In Set-up Time) slave 12 12 — 12 — 12 — ns 124 SCKT Edge to Word Select In Not Valid (WST In Hold Time) slave 12 12 — 12 — 12 — ns Note: 1. When the Frequency Ratio between Parallel and Serial clocks is 1:4 or greater 2. When the Frequency Ratio between Parallel and Serial clocks is 1:3 – 1:4 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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