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DSP56004ROM Datasheet(PDF) 58 Page - Freescale Semiconductor, Inc |
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DSP56004ROM Datasheet(HTML) 58 Page - Freescale Semiconductor, Inc |
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58 / 82 page  2-34 DSP56004/D, Rev. 3 MOTOROLA Specifications Serial Host Interface (SHI) I2C Protocol Timing 180 Data Hold Time tHD;DAT bypassed narrow wide 0 0 0 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — ns ns ns 182 SCL Low to Data Out Valid tVD;DAT bypassed narrow wide 2 × T C + 71 + tr 2 × T C + 244 + tr 2 × T C + 535 + tr — — — 349 522 813 — — — 339 512 803 — — — 344 507 798 ns ns ns 183 Stop Condition Set-up Time tSU;STO master slave bypassed narrow wide bypassed narrow wide 0.5 × t I 2CCP + TC + TH + 11 0.5 × t I 2CCP + TC + TH + 69 0.5 × t I 2CCP + TC + TH + 183 11 50 150 381 459 613 11 50 150 — — — — — — 359 440 592 11 50 150 — — — — — — 351 433 584 11 50 150 — — — — — — ns ns ns ns ns ns 184 HREQ In Deassertation to Last SCL Edge (HREQ In Set-up Time) master bypassed narrow wide 0 0 0 0 0 0 — — — 0 0 0 — — — 0 0 0 — — — ns ns ns 186 First SCL Sampling Edge to HREQ Output Deassertation slave bypassed narrow wide 3 × T C + TH + 32 3 × T C + TH + 209 3 × T C + TH + 507 — — — 102 279 577 — — — 85 262 560 — — — 75 252 550 ns ns ns 187 Last SCL Edge to HREQ Output Not Deasserted slave bypassed narrow wide 2 × T C + TH + 6 2 × T C + TH + 63 2 × T C + TH + 169 56 113 219 — — — 44 101 207 — — — 37 93.9 200 — — — ns ns ns 188 HREQ In Assertion to First SCL Edge master bypassed narrow wide tI2CCP + 2 × TC + 6 tI2CCP + 2 × TC + 6 tI2CCP + 2 × TC + 6 726 766 846 — — — 688 733 809 — — — 673 722 796 — — — ns ns ns Table 2-15 SHI Improved I2C Protocol Timing (Continued) Improved I2C (CL = 50 pF, RP = 2 kΩ) No. Char. Sym. Mode Filter Mode Expression 50 MHz2 66 MHz3 81 MHz4 U n i t Min Max Min Max Min Max Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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