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DSP56004ROM Datasheet(PDF) 57 Page - Freescale Semiconductor, Inc |
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DSP56004ROM Datasheet(HTML) 57 Page - Freescale Semiconductor, Inc |
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57 / 82 page ![]() Specifications Serial Host Interface (SHI) I2C Protocol Timing MOTOROLA DSP56004/D, Rev. 3 2-33 174 Start Condition Hold Time tHD;STA master slave bypassed narrow wide bypassed narrow wide 0.5 × t I 2CCP + 12 – tf 0.5 × t I 2CCP + 12 – tf 0.5 × t I 2CCP + 12 – tf 2 × T C + T H + 21 2 × T C + T H + 100 2 × T C + T H + 200 332 352 372 71 150 250 — — — — — — 318 340 378 59 138 238 — — — — — — 313 338 375 51.9 131 231 — — — — — — ns ns ns ns ns ns 175 SCL Low Period tLOW master slave bypassed narrow wide bypassed narrow wide 0.5 × t I 2CCP + 18 – tf 0.5 × t I 2CCP + 18 – tf 0.5 × t I 2CCP + 18 – tf 2 × T C + 74 + tr 2 × T C + 286 + tr 2 × T C + 586 + tr 338 358 378 352 564 864 — — — — — — 324 346 384 342 554 854 — — — — — — 319 344 381 337 536 849 — — — — — — ns ns ns ns ns ns 176 SCL High Period tHIGH master slave bypassed narrow wide bypassed narrow wide 0.5 × t I 2CCP + 2 × T C + 19 0.5 × t I 2CCP + 2 × T C + 144 0.5 × t I 2CCP + 2 × T C + 356 2 × T C + TH – 1 2 × T C + TH + 18 2 × T C + TH + 30 379 544 776 49 68 80 — — — — — — 375 523 773 37 56 68 — — — — — — 365 514 763 30 49 61 — — — — — — ns ns ns ns ns ns 177 SCL Rise Time Output1 Input tr 1.7 × R P × (CL + 20) 2000 — — 238 2000 — — 238 2000 — — 238 2000 ns ns 178 SCL Fall Time Output1 Input tf 20 + 0.1 × (CL– 50) 2000 — — 20 2000 — — 20 2000 — — 20 2000 ns ns 179 Data Set-up Time tSU;DAT bypassed narrow wide TC + 8 TC + 60 TC + 74 28 80 94 — — — 23 75 89 — — — 20 72 86 — — — ns ns ns Table 2-15 SHI Improved I2C Protocol Timing (Continued) Improved I2C (CL = 50 pF, RP = 2 kΩ) No. Char. Sym. Mode Filter Mode Expression 50 MHz2 66 MHz3 81 MHz4 U n i t Min Max Min Max Min Max Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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