DSP56004ROM datasheet(62/82 Pages) FREESCALE

62 / 82 page

2-38

DSP56004/D, Rev. 3

MOTOROLA

Specifications

On-Chip Emulation (OnCE

™) Timing

248

DR Assertion Width

•

to recover from WAIT

•

to recover from WAIT and enter Debug

mode

13 TC + 15

12 TC – 15

—

249

DR Assertion to DSO (ACK) Valid (Enter Debug

mode) After Asynchronous Recovery from Wait

State

17 TC

—ns

250A

DR Assertion Width to Recover from STOP2

• Stable External Clock, OMR Bit 6 = 0

• Stable External Clock, OMR Bit 6 = 1

• Stable External Clock, PCTL Bit 17 = 1

65548 TC + TL

20 TC + TL

13 TC + TL

250B

DR Assertion Width to Recover from STOP and

enter Debug mode2

• Stable External Clock, OMR Bit 6 = 0

• Stable External Clock, OMR Bit 6 = 1

• Stable External Clock, PCTL Bit 17 = 1

65549 TC + TL

21 TC + TL

14 TC + TL

—

251

DR Assertion to DSO (ACK) Valid (Enter Debug

mode) After Recovery from Stop State2

• Stable External Clock, OMR Bit 6 = 0

• Stable External Clock, OMR Bit 6 = 1

• Stable External Clock, PCTL Bit 17 = 1

65553 TC + TL

25 TC + TL

18 TC + TL

—

Note:

Maximum

Periodically sampled, not 100% tested

Figure 2-23 DSP56004 OnCE Serial Clock Timing

Table 2-17

OnCE Timing (Continued)

No.

Characteristics

All frequencies

Unit

Min

Max

DSCK

(input)

246

231

232

230

AA0277

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

DSP56004ROM Datasheet(PDF) 62 Page - Freescale Semiconductor, Inc

DSP56004ROM Datasheet(HTML) 62 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

Datasheet Download

Link URL