DS26519 datasheet(29/310 Pages) MAXIM

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DS26519 16-Port T1/E1/J1 Transceiver

29 of 310

NAME

TYPE

FUNCTION

MICROPROCESSOR INTERFACE

A13

C16

A12

F12

A11

A20

A10

G11

A21

F13

A22

H10

B19

H11

D15

G13

B20

Input

Address [13:0].

This bus selects a specific register in the DS26519 during

read/write access. A13 is the MSB and A0 is the LSB.

D[7]/

SPI_CPOL

Input

Data [7]/SPI Interface Clock Polarity

D[7]:

Bit 7 of the 16-bit or 8-bit data bus used to input data during register writes

and data outputs during register reads. Not driven when

CSB = 1.

SPI_CPOL:

This signal selects the clock polarity when SPI_SEL = 1. See Section

9.1.2 for detailed timing and functionality information. Default setting is low.

D[6]/

SPI_CPHA

Input

Data [6]/SPI Interface Clock Phase

D[6]:

Bit 6 of the 16-bit or 8-bit data bus used to input data during register writes

and data outputs during register reads. Not driven when

CSB = 1.

SPI_CPHA:

This signal selects the clock phase when SPI_SEL = 1. See Section

9.1.2 for detailed timing and functionality information. Default setting is low.

D[5]/

SPI_SWAP

AA6

Input

Data [5]/SPI Bit Order Swap

D[5]:

Bit 5 of the 16-bit or 8-bit data bus used to input data during register writes

and data outputs during register reads. Not driven when

CSB = 1.

SPI_SWAP:

This signal is active when SPI_SEL = 1. The address and data bit

order is swapped when SPI_SWAP is high. The R/W and B bit positions are

never changed in the control word.

0 = LSB is transmitted and received first.

1 = MSB is transmitted and received first.

D[4]

T14

Input

Data [4].

Bit 4 of the 8-bit data bus used to input data during register writes and

data outputs during register reads. Not driven when

CSB = 1.

D[3]

AB5

Input

Data [3].

Bit 3 of the 8-bit data bus used to input data during register writes and

data outputs during register reads. Not driven when

CSB = 1.

D[2]/

SPI_SCLK

R14

Input

Data [2]/SPI Serial Interface Clock

D[2]:

Bit 2 of the 8-bit data bus used to input data during register writes and data

outputs during register reads. Not driven when

CSB = 1.

SPI_SCLK:

SPI Serial Clock Input when SPI_SEL = 1.

D[1]/

SPI_MOSI

AA5

Input

Data [1]/SPI Serial Interface Data Master Out-Slave In

D[1]

: Bit 1 of the 8-bit data bus used to input data during register writes, and data

outputs during register reads. Not driven when

CSB = 1.

SPI_MOSI:

SPI Serial Data Input (Master Out-Slave In) when SPI_SEL = 1.

D[0]/

SPI_MISO

P14

Input

Data [0]/SPI Serial Interface Data Master In-Slave Out

D[0]:

Bit 0 of the 8-bit data bus used to input data during register writes and data

outputs during register reads. Not driven when

CSB = 1.

SPI_MISO:

SPI Serial Data Output (Master In-Slave Out) when SPI_SEL = 1.

CSB

Chip-Select Bar.

This active-low signal is used to qualify register read/write

accesses. The

RDB/DSB and WRB signals are qualified with CSB.

RDB/

DSB

Read-Data Bar/Data-Strobe Bar.

This active-low signal along with

CSB qualifies

read access to one of the DS26519 registers. The DS26519 drives the data bus

with the contents of the addressed register while

RDB and CSB are low.

DS26519 Datasheet(PDF) 29 Page - Maxim Integrated Products

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