DS26519 datasheet(30/310 Pages) MAXIM

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DS26519 16-Port T1/E1/J1 Transceiver

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NAME

TYPE

FUNCTION

WRB/

RWB

R13

Input

Write-Read Bar/Read-Write Bar.

This active-low signal along with

CSB qualifies

write access to one of the DS26519 registers. Data at D[7:0] is written into the

addressed register at the rising edge of

WRB while CSB is low.

INTB

Output/

Tri-

Stateable

Interrupt Bar.

This active-low output is asserted when an unmasked interrupt

event is detected.

INTB will be deasserted (and tri-stated) when all interrupts

have been acknowledged and serviced. Extensive mask bits are provided at the

global level, framer, LIU, and BERT level.

SPI_SEL

Input

SPI Serial Bus Mode Select

0 = Parallel Bus Mode

1 = SPI Serial Bus Mode

BTS

U15

Input

Bus Type Select.

Set high to select Motorola bus timing, low to select Intel bus

timing. This pin controls the function of the

RDB/DSB and WRB pins. Note: If SPI

mode is selected by the SPI_SEL pin, this pin must be tied low.

SYSTEM INTERFACE

MCLK

F11

Input

Master Clock.

This is an independent free-running clock whose input can be a

multiple of 2.048MHz ±50ppm or 1.544MHz ±50ppm. The clock selection is

available by bits MPS0 and MPS1 and FREQSEL. Multiple of 2.048MHz can be

internally adapted to 1.544MHz. Multiple of 1.544MHz can be adapted to

2.048MHz. Note that TCLKn must be 2.048MHz for E1 and 1.544MHz for T1/J1

operation. See Table 10-14.

RESETB

T16

Input

Reset Bar.

Active-low reset. This input forces the complete DS26519 reset. This

includes reset of the registers, framers, and LIUs.

REFCLKIO

A18

Input/

Output

Reference Clock Input/Output

Input:

A 2.048MHz or 1.544MHz clock input. This clock can be used to generate

the backplane clock. This allows for the users to synchronize the system

backplane with the reference clock. The other options for the backplane clock

reference are LIU-received clocks or MCLK.

Output:

This signal can also be used to output a 1.544MHz or 2.048MHz

reference clock. This allows for multiple DS26519s to share the same reference

for generation of the backplane clock. Hence, in a system consisting of multiple

DS26519s, one can be a master and others a slave using the same reference

clock.

TEST

DIGIOEN

A14

Input,

Pullup

Digital Enable.

When this pin and

JTRST are pulled low, all digital I/O pins are

placed in a high-impedance state. If this pin is high the digital I/O pins operate

normally. This pin must be connected to VDD for normal operation.

JTRST

Input,

Pullup

JTAG Reset.

JTRST is used to asynchronously reset the test access port

controller. After power-up,

JTRST must be toggled from low to high. This action

sets the device into the JTAG DEVICE ID mode. Pulling

JTRST low restores

normal device operation.

JTRST is pulled high internally via a 10k

Ω resistor

operation. If boundary scan is not used, this pin should be held low.

JTMS

Input,

Pullup

JTAG Mode Select.

This pin is sampled on the rising edge of JTCLK and is used

to place the test access port into the various defined IEEE 1149.1 states. This pin

has a 10k

Ω pullup resistor.

JTCLK

Input

JTAG Clock.

This signal is used to shift data into JTDI on the rising edge and out

of JTDO on the falling edge.

JTDI

Input,

Pullup

JTAG Data In.

Test instructions and data are clocked into this pin on the rising

edge of JTCLK. This pin has a 10k

Ω pullup resistor.

JTDO

Output,

High

Impedance

JTAG Data Out.

Test instructions and data are clocked out of this pin on the

falling edge of JTCLK. If not used, this pin should be left unconnected.

SCANEN

Input

Scan Enable.

When low, the device is in normal operation. User should tie low.

SCANMODE

V18

Input

Scan Mode.

When low, normal operational clocks are used to clock the flip flops.

User should tie low.

TST_TA1

TST_TB1

TST_TC1

TST_RA1

TST_RB1

TST_RC1

Output

LIU Test Points.

Test signals from LIU 1. User should leave unconnected.

DS26519 Datasheet(PDF) 30 Page - Maxim Integrated Products

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