DS26519 datasheet(6/310 Pages) MAXIM

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DS26519 16-Port T1/E1/J1 Transceiver

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Figure 11-17. E1 Receive-Side Timing.................................................................................................................... 278

Figure 11-18. E1 Receive-Side Boundary Timing (Elastic Store Disabled) ............................................................ 278

Figure 11-19. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)............................................ 279

Figure 11-20. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)............................................ 279

Figure 11-21. E1 Receive-Side Interleave Bus Operation—BYTE Mode ............................................................... 280

Figure 11-22. E1 Receive-Side Interleave Bus Operation—FRAME Mode ............................................................ 281

Figure 11-23. E1 Receive-Side RCHCLKn Gapped Mode During Channel 1 ........................................................ 281

Figure 11-24. E1 Transmit-Side Timing................................................................................................................... 282

Figure 11-25. E1 Transmit-Side Boundary Timing (Elastic Store Disabled) ........................................................... 282

Figure 11-26. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 283

Figure 11-27. E1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 283

Figure 11-28. E1 Transmit-Side Interleave Bus Operation—BYTE Mode .............................................................. 284

Figure 11-29. E1 Transmit-Side Interleave Bus Operation—FRAME Mode ........................................................... 285

Figure 11-30. E1 G.802 Timing ............................................................................................................................... 286

Figure 11-31. E1 Transmit-Side TCHCLKn Gapped Mode During Channel 1 ........................................................ 286

Figure 13-1. SPI Interface Timing Diagram ............................................................................................................. 290

Figure 13-2. Intel Bus Read Timing (BTS = 0) ........................................................................................................ 292

Figure 13-3. Intel Bus Write Timing (BTS = 0)......................................................................................................... 292

Figure 13-4. Motorola Bus Read Timing (BTS = 1) ................................................................................................. 293

Figure 13-5 Motorola Bus Write Timing (BTS = 1) .................................................................................................. 293

Figure 13-6. Receive Framer Timing—Backplane (T1 Mode)................................................................................. 295

Figure 13-7. Receive-Side Timing—Elastic Store Enabled (T1 Mode) ................................................................... 296

Figure 13-8. Receive Framer Timing—Line Side .................................................................................................... 296

Figure 13-9. Transmit Formatter Timing—Backplane ............................................................................................. 298

Figure 13-10. Transmit Formatter Timing—Elastic Store Enabled.......................................................................... 298

Figure 13-11. BPCLKn Timing................................................................................................................................. 299

Figure 13-12. Transmit Formatt Timing—Line Side ................................................................................................ 299

Figure 13-13. JTAG Interface Timing Diagram........................................................................................................ 300

Figure 14-1. JTAG Functional Block Diagram ......................................................................................................... 302

Figure 14-2. TAP Controller State Diagram............................................................................................................. 305

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