DS26519 datasheet(46/310 Pages) MAXIM

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DS26519 16-Port T1/E1/J1 Transceiver

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9.8.1.7 Mapping E1 Channels onto a 1.544MHz Backplane

The user can use the RSCLKM bit in RIOCR.4 to enable the receive elastic store to operate with a 1.544MHz

backplane (24 channels / frame + F-bit). In this mode the user can choose which of the E1 time slots will be

ignored (not transmitted onto RSERn) by programming the Receive Blank Channel Select registers (RBCS1–4). A

logic 1 in the associated bit location will cause the elastic store to ignore the incoming E1 data for that channel.

Typically, the user will want to program eight channels to be ignored. The default (power-up) configuration will

ignore channels 25 to 32, so that the first 24 E1 channels are mapped into the 24 channels of the 1.544MHz

backplane. In this mode the F-bit location at RSERn is always set to 1.

For example, if the user wants to ignore E1 time slots 0 (channel 1) and TS 16 (channel 17), the RBCS registers

would be programmed as follows:

RBCS1 = 01h

RBCS2 = 00h

RBCS3 = 01h

RBCS4 = FCh

9.8.2

IBO Multiplexing

The DS26519 offers two methods of multiplexing data streams onto a high-speed backplane bus. The traditional

method of IBO operation that allows the user to gang signals together on the PCB is supported. RSERn and RSIGn

will tri-state at the appropriate times to allow the ganging of these signals together.

The default method multiplexes the data streams internally and then outputs them on one pin, i.e., RSER1. For

example, if the user wants to multiplex RSER[1:8] together to make a 16MHz high-speed bus, the data stream will

be output on RSER1 only.

The selection between external ganging and internal multiplexing is made via GTCR1.GIBO.

Note that in IBO mode, the channel block signals TCHBLKn and RCHBLKn are referenced to as TSYSCLKn and

RSYSCLKn.

Figure 9-12, Figure 9-13, and Figure 9-14 show the equivalent internal circuit for each IBO mode. These figures

only show channels 1–8. Channels 9–16 have their own identical IBO circuitry as Channels 1–8. Table 9-5

describes the pin function changes for each mode of the IBO multiplexer.

Table 9-5. Registers Related to the IBO Multiplexer

FRAMER 1

ADDRESSES

FUNCTION

Global Transceiver Control

00F0h

This is a global register used to specify ganged operation

for the IBO.

Global Framer Control Register 1

(GFCR1)

00F1h

This global register defines the number of devices per

bus and bus speed.

Receive Interleave Bus Operation

Control Register (RIBOC)

088h

This register configures the per-port IBO enable and type

of interleaving (channel vs. frame).

Transmit Interleave Bus

Operation Control Register

(TIBOC)

188h

This register configures the per-port IBO enable and type

of interleaving (channel vs. frame).

Note: The addresses shown above are for Framer 1.

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