MPXY8300 datasheet(44/164 Pages) FREESCALE

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MPXY8300 Series

Sensors

Freescale Semiconductor

SECTION 6 PARALLEL INPUT/OUTPUT CONTROL

This section explains software controls related to parallel input/output (I/O) and pin control. The MPXY8300 Series has one I/O

ports which includes a total of 6 general-purpose I/O pins. See Section 2, for more information about pin assignments and

external hardware considerations of these pins.

All of these pins are shared with on-chip peripheral functions as shown in Figure 2-1. The peripheral modules have priority over

the parallel I/O so that when a peripheral is enabled, the parallel I/O functions associated with the shared pins are disabled. After

reset, the shared peripheral functions are disabled so that the pins are controlled by the parallel I/O and are configured as inputs

(PTADDn = 0) with pull-up devices disabled (PTAPEn = 0).

NOTE

To avoid extra current drain from floating input pins, the user’s reset initialization routine in the application

program must either enable on-chip pull-up devices or change the direction of unconnected pins to outputs so

the pins do not float.

Reading and writing of parallel I/O is performed through the port data registers. The direction, either input or output, is controlled

through the port data direction registers. The parallel I/O port function for an individual pin is illustrated in the block diagram in

Figure 1-1.

The data direction control bit (PTADDn) determines whether the output buffer for the associated pin is enabled, and also controls

the source for port data register reads. The input buffer for the associated pin is always enabled unless the pin is enabled as an

analog function.

When a shared digital function is enabled for a pin, the output buffer is controlled by the shared function. However, the data

direction register bit still controls the source for reads of the port data register.

When a shared analog function is enabled for a pin, both the input and output buffers are disabled. A value of 0 is read for any

port data bit where the bit is an input (PTADDn = 0) and the input buffer is disabled. In general, whenever a pin is shared with

both an alternate digital function and an analog function, the analog function has priority such that if both the digital and analog

functions are enabled, the analog function controls the pin.

It is a good programming practice to write to the port data register before changing the direction of a port pin to become an output.

This ensures that the pin will not be driven momentarily with an old data value that happened to be in the port data register.

An internal pull-up device can be enabled for each port pin by setting the corresponding bit in one of the pull-up enable registers

(PTAPEn). The pull-up device is disabled if the pin is configured as an output by the parallel I/O control logic or any shared

peripheral function regardless of the state of the corresponding pull-up enable register bit. The pull-up device is also disabled if

the pin is controlled by an analog function.

6.1

Pin Behavior in Stop Modes

Pin behavior following execution of a STOP instruction depends on the stop mode that is entered. An explanation of pin behavior

for the various stop modes follows:

•

In stop1 mode, all internal registers including general purpose I/O control and data registers are powered off. Each of

the pins assumes its default reset state (output buffer and internal pull-up disabled). Upon exit from stop1, all pins must

be reconfigured the same as if the MCU had been reset.

•

Stop2 mode is a partial power-down mode, whereby I/O latches are maintained in their state as before the STOP

instruction was executed. CPU register status and the state of I/O registers must be saved in RAM before the STOP

instruction is executed to place the MCU in stop2 mode. Upon recovery from stop2 mode, before accessing any I/O, the

user must examine the state of the PPDF bit in the SPMSC2 register. If the PPDF bit is 0, I/O must be initialized as if a

power on reset had occurred. If the PPDF bit is 1, I/O data previously stored in RAM, before the STOP instruction was

executed, peripherals may require being initialized and restored to their pre-stop condition. The user must then write a

1 to the PPDACK bit in the SPMSC2 register. Access to I/O is now permitted again in the user’s application program.

•

In stop3 mode, all pin states are maintained because internal logic stays powered up. Upon recovery, all pin functions

are the same as before entering stop3.

MPXY8300 Datasheet(PDF) 44 Page - Freescale Semiconductor, Inc

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