MPXY8300 datasheet(71/164 Pages) FREESCALE

71 / 164 page

MPXY8300 Series

Sensors

Freescale Semiconductor

When background mode is active, the timer counter and the coherency mechanism are frozen such that the buffer latches remain

in the state they were in when the background mode became active even if one or both bytes of the counter are read while

background mode is active.

9.3.3

Timer x Counter Modulo Registers (TPMMODH:TPMMODL)

The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM counter reaches the modulo

value, the TPM counter resumes counting from 0x0000 at the next clock (CPWMS = 0) or starts counting down (CPWMS = 1),

and the overflow flag (TOF) becomes set. Writing to TPMMODH or TPMMODL inhibits TOF and overflow interrupts until the other

byte is written. Reset sets the TPM counter modulo registers to 0x0000, which results in a free-running timer counter (modulo

disabled).

It is good practice to wait for an overflow interrupt so both bytes of the modulo register can be written well before a new overflow.

An alternative approach is to reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when

the first counter overflow will occur.

9.3.4

Timer x Channel n Status and Control Register (TPMCnSC)

TPMCnSC contains the channel interrupt status flag and control bits that are used to configure the interrupt enable, channel

configuration, and pin function.

Bit 15

Bit 8

Reset

Figure 9-5 Timer x Counter Modulo Register High (TPMMODH)

Bit 7

Bit 0

Reset

Figure 9-6 Timer x Counter Modulo Register Low (TPMMODL)

CHnF

CHnIE

MSnB

MSnA

ELSnB

ELSnA

Reset

= Unimplemented or Reserved

Figure 9-7 Timer x Channel n Status and Control Register (TPMCnSC)

MPXY8300 Datasheet(PDF) 71 Page - Freescale Semiconductor, Inc