MPXY8300 datasheet(73/164 Pages) FREESCALE

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MPXY8300 Series

Sensors

Freescale Semiconductor

9.3.5

Timer x Channel Value Registers (TPMCnVH:TPMCnVL)

These read/write registers contain the captured TPM counter value of the input capture function or the output compare value for

the output compare or PWM functions. The channel value registers are cleared by reset.

In input capture mode, reading either byte (TPMCnVH or TPMCnVL) latches the contents of both bytes into a buffer where they

remain latched until the other byte is read. This latching mechanism also resets (becomes unlatched) when the TPMCnSC

In output compare or PWM modes, writing to either byte (TPMCnVH or TPMCnVL) latches the value into a buffer. When both

bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. This latching

mechanism may be manually reset by writing to the TPMCnSC register.

This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler implementations.

9.4

Functional Description

All TPM functions are associated with a main 16-bit counter that allows flexible selection of the clock source and prescale divisor.

A 16-bit modulo register also is associated with the main 16-bit counter in the TPM. Each TPM channel is optionally associated

with an MCU pin and a maskable interrupt function.

The TPM has center-aligned PWM capabilities controlled by the CPWMS control bit in TPMSC. When CPWMS is set to 1, timer

counter TPMCNT changes to an up-/down-counter and all channels in the associated TPM act as center-aligned PWM channels.

When CPWMS = 0, each channel can independently be configured to operate in input capture, output compare, or buffered edge-

aligned PWM mode.

The following sections describe the main 16-bit counter and each of the timer operating modes (input capture, output compare,

edge-aligned PWM, and center-aligned PWM). Because details of pin operation and interrupt activity depend on the operating

mode, these topics are covered in the associated mode sections.

9.4.1

Counter

All timer functions are based on the main 16-bit counter (TPMCNTH:TPMCNTL). This section discusses selection of the clock

source, up-counting vs. up-/down-counting, end-of-count overflow, and manual counter reset.

After any MCU reset, CLKSB:CLKSA = 0:0 so no clock source is selected and the TPM is inactive. Normally, CLKSB:CLKSA

would be set to 0:1 so the bus clock drives the timer counter. The clock source for each of the TPM can be independently selected

to be off, the bus clock (BUSCLK), the fixed system clock (XCLK), or an external input. The maximum frequency allowed for the

external clock option is one-fourth the bus rate. Refer to Section 9.3.1 and Table 9-4 for more information about clock source

selection.

When the microcontroller is in active background mode, the TPM temporarily suspends all counting until the microcontroller

returns to normal user operating mode. During stop mode, all TPM clocks are stopped; therefore, the TPM is effectively disabled

until clocks resume. During wait mode, the TPM continues to operate normally.

The main 16-bit counter has two counting modes. When center-aligned PWM is selected (CPWMS = 1), the counter operates in

up-/down-counting mode. Otherwise, the counter operates as a simple up-counter. As an up-counter, the main 16-bit counter

counts from 0x0000 through its terminal count and then continues with 0x0000. The terminal count is 0xFFFF or a modulus value

in TPMMODH:TPMMODL.

Bit 15

Bit 8

Reset

Figure 9-8 Timer x Channel Value Register High (TPMCnVH)

Bit 7

Bit 0

Reset

Figure 9-9 Timer Channel Value Register Low (TPMCnVL)

MPXY8300 Datasheet(PDF) 73 Page - Freescale Semiconductor, Inc

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