MPXY8300 datasheet(77/164 Pages) FREESCALE

77 / 164 page

MPXY8300 Series

Sensors

Freescale Semiconductor

9.5.3

Channel Event Interrupt Description

The meaning of channel interrupts depends on the current mode of the channel (input capture, output compare, edge-aligned

PWM, or center-aligned PWM).

When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select rising edges, falling edges, any

edge, or no edge (off) as the edge that triggers an input capture event. When the selected edge is detected, the interrupt flag is

set. The flag is cleared by the 2-step sequence described in Section 9.5.1.

When a channel is configured as an output compare channel, the interrupt flag is set each time the main timer counter matches

the 16-bit value in the channel value register. The flag is cleared by the 2-step sequence described in Section 9.5.1.

9.5.4

PWM End-of-Duty-Cycle Events

For channels that are configured for PWM operation, there are two possibilities:

•

When the channel is configured for edge-aligned PWM, the channel flag is set when the timer counter matches the

channel value register that marks the end of the active duty cycle period.

•

When the channel is configured for center-aligned PWM, the timer count matches the channel value register twice

during each PWM cycle. In this CPWM case, the channel flag is set at the start and at the end of the active duty cycle,

which are the times when the timer counter matches the channel value register.

The flag is cleared by the 2-step sequence described in Section 9.5.1.

MPXY8300 Datasheet(PDF) 77 Page - Freescale Semiconductor, Inc