PCA9421 datasheet(16/66 Pages) NXP

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NXP Semiconductors

PCA9421

Power management IC for low-power microcontroller applications

8.11.5 BUCK2 (SW2, system buck regulator)

The SW2 output voltage can be programmed via I2C register from 1.5 V to 2.1 V, or from 2.7 V to 3.3 V in both

at 25 mV/step and is capable of providing up to 500 mA loading. The application circuit uses a 2.2 µH inductor

and 10 µF output capacitor.

In SW2, a pass-through mode is implemented. When its input (ASYS) is close to the output voltage (within

typical 200 mV), the SW2 enters the pass-through mode operation; the high-side switch is fully turned on and

the low-side switch is turned off, and the output voltage can be calculated as input voltage – (RDSON*ILOAD),

where RDSON is the on-resistance of the high-side switch, and the ILOAD refers to the load current. When the

input voltage rises again, so that the voltage different between input and output crosses the typical 250 mV

threshold, the SW2 exits the pass-through mode and re- enters the normal switching mode operation.

This regulator implements an output current limit protection. When the inductor peak current reaches ILIM(SW2) it

enters a cyclic mechanism where the inductor current ramps down until it reaches 0 A. The regulator increases

inductor current and retries start up. This cyclic current limiting stops once the overcurrent condition is removed.

The output voltage collapses during the cyclic current limiting.

While SW2 operates in pass-through mode, protection features such as over-current protection are also

implemented as well.

aaa-033081

VSW2_Regulation

VPSYS2

(VPSYS2 - VSW2_Regulation)=200mV

50mV

SW2 in regulation mode

SW2 in pass-through mode

SW2 in regulation mode

Delta V=RRDS_ON_High_side x ILOAD

Delta V

Figure 8. Pass-Through mode of BUCK2 (SW2)

8.11.6 LDO1 (always-on LDO)

The LDO1 (Always-on LDO) output can be programmed from 1.7 V to 1.9 V at 25 mV step, depending on the

system requirements (selectable through I2C register). Typically, a 1 µF/6.3 V MLCC output capacitor providing

at least 1 mA loading capability is needed.

LDO1 operates based on the principle of hysteretic on/off regulation. The LDO1 output voltage is generated

from a frequent activation/deactivation of the output stage connecting VIN_AUX to the LDO1 output depending

on the programmed output voltage for LDO1. The ripple frequency and amplitude greatly depends on the load

current and external capacitance. The greater the load current, the higher the on/off activation of this output

stage to ensure LDO1 stays within the defined output voltage accuracy specified in the electrical specification

section. LDO1 is powered by the greater of ASYS or VBAT_BKUP.

SW_RST event will not shut down LDO1, but sets LDO1 to default value. Watchdog Reset will not shut down

LDO1, but changes LDO1 to Mode 0 setting. Hardware Reset (ON Long Press) shuts down LDO1 and recycles

power up to default output voltage.

This regulator implements an output current limit protection. As output current is limited by IOUT_LDO1_LIMIT, the

output voltage collapses if the load current is higher than IOUT_LDO1_LIMIT. Once the overcurrent is removed the

regulator restarts automatically.

PCA9421

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.0 — 16 October 2023

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