PCA9421 datasheet(63/66 Pages) NXP

63 / 66 page

NXP Semiconductors

PCA9421

Power management IC for low-power microcontroller applications

Tables

Tab. 1.

Ordering information ..........................................2

Tab. 2.

Ordering options ................................................2

Tab. 3.

Pin description ...................................................5

Tab. 4.

Mode selection by external pins

(MODESEL0, MODESEL1) .............................12

Tab. 5.

Regulator summary .........................................13

Tab. 6.

Device level protection features ...................... 17

Tab. 7.

I2C target address .......................................... 18

Tab. 8.

Tab. 9.

DEV_INFO register bit description .................. 20

Tab. 10. TOP_INT register bit description ..................... 20

Tab. 11. Sub_INT0 register bit description ....................21

Tab. 12. Sub_INT0_Mask bit description ...................... 22

Tab. 13. Sub_INT1 register bit description ....................22

Tab. 14. Sub_INT1_Mask register bit description ..........23

Tab. 15. Sub_INT2 register bit description ....................23

Tab. 16. Sub_INT2_Mask register bit description ..........24

Tab. 17. TOP_CNTL0 register bit description ................24

Tab. 18. TOP_CNTL1 register bit description ................25

Tab. 19. TOP_CNTL2 register bit description ................26

Tab. 20. TOP_CNTL3 register bit description ................27

Tab. 21. TOP_CNTL4 register bit description ................27

Tab. 22. VIN_PWR Status_0 register bit description .....28

Tab. 23. VIN_PWR Status_1 register bit description .....28

Tab. 24. REG_STATUS register bit description .............28

Tab. 25. ACT_DISCHARGE_CNTL register bit

description ....................................................... 29

Tab. 26. MODECFG_0_0 register bit description .......... 29

Tab. 27. SW1 output voltage for Mode Setting 0 ...........30

Tab. 28. MODECFG_0_1 register bit description .......... 30

Tab. 29. SW2 default output voltage for mode

setting 0 ...........................................................31

Tab. 30. MODECFG_0_2 register bit description .......... 31

Tab. 31. LDO1 default output voltage for mode

setting 0 ...........................................................32

Tab. 32. MODECFG_0_3 register bit description .......... 32

Tab. 33. LDO2 default output voltage for mode

setting 0 ...........................................................32

Tab. 34. MODECFG_1_0 register bit description .......... 33

Tab. 35. SW1 output voltage for Mode Setting 1 ...........33

Tab. 36. MODECFG_1_1 register bit description .......... 34

Tab. 37. SW2 default output voltage for mode

setting 1 ...........................................................34

Tab. 38. MODECFG_1_2 register bit description .......... 35

Tab. 39. LDO1 default output voltage for mode

setting 1 ...........................................................35

Tab. 40. MODECFG_1_3 register bit description .......... 35

Tab. 41. LDO2 default output voltage for mode

setting 1 ...........................................................36

Tab. 42. MODECFG_2_0 register bit description .......... 36

Tab. 43. SW1 output voltage for Mode Setting 2 ...........36

Tab. 44. MODECFG_2_1 register bit description .......... 37

Tab. 45. SW2 default output voltage for mode

setting 2 ...........................................................37

Tab. 46. MODECFG_2_2 register bit description .......... 38

Tab. 47. LDO1 default output voltage for mode

setting 2 ...........................................................38

Tab. 48. MODECFG_2_3 register bit description .......... 38

Tab. 49. LDO2 default output voltage for mode

setting 2 ...........................................................39

Tab. 50. MODECFG_3_0 register bit description .......... 39

Tab. 51. SW1 output voltage for mode setting 3 ........... 39

Tab. 52. MODECFG_3_1 register bit description .......... 40

Tab. 53. SW2 default output voltage for mode

setting 3 ...........................................................40

Tab. 54. MODECFG_3_2 register bit description .......... 41

Tab. 55. LDO1 default output voltage for mode

setting 3 ...........................................................41

Tab. 56. MODECFG_3_3 register bit description .......... 41

Tab. 57. LDO2 default output voltage for mode

setting 3 ...........................................................42

Tab. 58. RESET monitor register bit description ........... 42

Tab. 59. Limiting values ................................................ 44

Tab. 60. Limiting values ................................................ 44

Tab. 61. Recommended operating conditions ...............44

Tab. 62. EC table for Top level ..................................... 45

Tab. 63. EC table for BUCK1 (SW1) .............................48

Tab. 64. EC table for BUCK2 (SW2) ...........................50

Tab. 65. EC table for LDO1 .......................................... 51

Tab. 66. EC table for LDO2 .......................................... 52

Tab. 67. EC table for I2C and Logic ..............................53

Tab. 68. Dimensions and quantities .............................. 58

Tab. 69. Carrier tape dimensions ..................................58

Tab. 70. Dimensions and quantities .............................. 59

Tab. 71. Carrier tape dimensions ..................................59

Tab. 72. Revision history ...............................................60

Figures

Fig. 1.

Simplified block diagram ................................... 3

Fig. 2.

PCA9421BS pinout (HVQFN24) – top view .......4

Fig. 3.

PCA9421UK pinout (WLCSP25) – top view ...... 4

Fig. 4.

System configuration diagram; i.MXRT

series .................................................................7

Fig. 5.

System configuration diagram; K4-family

MCU .................................................................. 8

Fig. 6.

Power control state diagram ............................. 9

Fig. 7.

Power-up/down sequence ...............................15

Fig. 8.

Pass-Through mode of BUCK2 (SW2) ............16

Fig. 9.

Package outline SOT905-1 (HVQFN24) ......... 55

Fig. 10.

Package outline SOT1401-4 (WLCSP25)

(1 of 2) ............................................................ 56

Fig. 11.

Package outline SOT1401-4 (WLCSP25)

(2 of 2) ............................................................ 57

Fig. 12.

Product orientation in carrier tape ................... 58

Fig. 13.

Carrier tape dimensions ..................................58

Fig. 14.

Product orientation in carrier tape ................... 59

PCA9421

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.0 — 16 October 2023

63 / 66

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